December 13 Report:
– Intel’s next-gen SoC manufacturing process will be able to deliver the next Bay Trail Atom only for 2014 products (with higher end Haswell for H2 2013), and it is just a 26nm process in terminology used by the foundry industry not a 22nm one touted by Intel

Lesson from that: Intel may speak about its “22 nm SoC process” but given the late entry of its 32nm SoC process Atom product (Cover Trail) it would be better to assume that with Windows 8 tablets based on that it will affect only the 2014 tablet market, not earlier. This is what the latest leaks are suggesting as well. Meanwhile expect a low-power Haswell ULT based tablet PC push in the H2 2013 as described already in my Intel Haswell: “Mobile computing is not limited to tiny, low-performing devices” [Nov 15 – Dec 11, 2012] post. As for the next year the real question is Can VIA Technologies save the mobile computing future of the x86 (x64) legacy platform? [this same blog of mine, Nov 23, 2012] For this watch what Allwinner vis-à-vis HTC on 2013 International CES [this same blog of mine, Dec 11, 2012] could bring in that respect, something much more than what is described in Allwinner A31 SoC is here with products and the A20 SoC is coming [USD 99 Allwinner blog of mine, Dec 10, 2012] or in $99 Android 4.0.3 7” IPS tablet with an Allwinner SoC capable of 2160p Quad HD and built-in HDMI–another inflection point, from China again [this same blog, Dec 3, 2012].    

– end of life of planar transistor and need to move to FinFET, but meanwhile FD-SOI to the rescue
– ARM Physical IP division via its upcoming IP is preparing with its foundry partners (TSMC, GLOBALFOUNDRIES and Samsung) an easier transition to FinFET

September 27 report:
– TSMC’s View of the Semiconductor IP Ecosystem
– Overall semiconductor IP market overview
– The CEVA case
– When sticking with the “Goliath”: ARM Holdings Plc
– When sticking with a “David”: CAST Inc.

Note: I am not discussing at all the most important development of the 64-bit ARM introductions as will devote to it a separate composite trend-tracking post on this blog.

Warning: These two reports are rather comprehensive and extensive on the given subject. When you will read these through your reward will be a deep and wide ranging understanding of this most actual issue for understanding the upcoming very dramatic changes in the further development of the whole ICT industry. To illustrate only some of the most related topics here is a copy of tags for this post:
14 nm, 14nm, 20 nm, 20nm, 22 nm, 22nm, 28 nm, 28nm, 3D devices, Allwinner, AndesCore, ARM Artisan IP, ARM Holdings, ARM Physical IP division, Artisan Physical IP Platform,Atom, BA22-AP, Bay Trail, Beyond BA22, big.LITTLE Processing, bulk CMOS, CAST Inc., CAST IP, CEVA, choice IP partner, Cortex A15, Cortex-A7, EnSilica eSi-3250, Fastec Imaging Corporation, Fastec TS3, FD-SOI, finFET,foundries, foundry and IP business model, foundry business, Freescale, Freescale ColdFire, general-purpose foundry business, GlobalFoundries, Haswell, Haswell-ULT, in-house IP blocks, inflection points, Intel, Intellectual Property, interface products, Internet of Things, IOT, IP suppliers, Kinetis, LEON3, licensable IP blocks, Lincroft, logic products, mainstream CMOS, Mali, MarketsandMarkets, MediaTek, memory compilers, MIPS32, mobile computing,Motomic, MT6588, MT6589, OpenRISC, planar transistor, POP, prime IP partners, Processor Optimization Pack,reusable subsystems, Samsung, semiconductor design, semiconductor intellectual property market, semiconductor IP, semiconductor IP ecosystem, semiconductor IP market, semiconductor IP revenue, silicon IP market, SoC manufacturing process, SoC process, Sodaville, SOI, standard cells, standard industry IP blocks, STMicroelectronics,system IP, tablet PC, transistor designs, Tri-Gate, Tri-Gate transistor, TSMC, TSMC IP Alliance, TSMC IP portfolio,TSMC Soft-IP Alliance, UMC, VIA Technologies, Z670

December 13 Report

– Intel’s next-gen SoC manufacturing process will be able to deliver the next Atom only for 2014 products (with higher end Haswell for H2 2013), and it is just a 26nm process in terminology used by the foundry industry not a 22nm one touted by Intel

Intel progressing in development of 14nm technology, says CTO [DIGITIMES, Dec 5, 2011]

Intel CTO Justin Rattner on December 4 said that Intel’s development of 14nm technology is on schedule with volume production to kick off in one to two years and development of 18-inch wafers is under way through cooperation with partners.

Rattner also noted that Intel’s aggressiveness over technology advancement will allow Moore’s Law to extend for another 10 years.

At the end of 2013, Intel will enter the generation of 14nm CPUs (P1272) and SoCs (1273), while expanding its investments at its D1X Fab in Oregon, and Fab 42 in Arizona, the US and Fab 24 in Ireland, and will gradually enter 10nm, 7nm and 5nm process generations starting 2015.

As for Intel’s competitors, Samsung is already set to enter 20nm in 2013 and is already working on its 14nm node, while Taiwan Semiconductor Manufacturing Company’s (TSMC) 20nm process [planar, i.e bulk CMOS, see below] will enter small volume production in the second half of 2013 with the first 3D-based FPGA chips to also start.

Globalfoundries has previously announced its 14nm FinFET process will start pilot production at the end of 2013 and enter mass production in 2014.

As for 18-inch wafers, Intel has invested in Holland-based ASML for its EUV technology, and related technologies are expected to start entering production in 2017.

Intel Has No Process Advantage In Mobile, says ARM CEO [Mannerisms on Electronics Weekly, Oct 24, 2012]

Intel has no advantage in IC manufacturing when it comes to manufacturing processes used for mobile ICs, Warren East, CEO of ARM, tells EW.

“This time last year there was a lot of noise from the Intel camp about their manufacturing superiority,” says East, “we’re sceptical about this because, while the ARM ecosystem was shipping on 28nm, Intel was shipping on 32nm. So I don’t see where they’re ahead.”

Furthermore, with the foundries accelerating their process development timescales, it looks increasingly unlikely that Intel will be able to find any advantage on mobile process technology in the future.

“We’re supporting all the independent foundries,” says East. That includes 20nm planar bulk CMOS and 16nm finfet at TSMC; 20nm planar bulk CMOS and 14nm finfet at Samsung and 20nm planar bulk CMOS, 20nm FD-SOI and 14nm finfet at Globalfoundries.

It gives the ARM ecosystem a formidable array of processes to choose from. “I’m no better equipped to judge which of these processes will be more successful than anyone else,” says East, “our approach is to be process agnostic.”

The important thing is that the foundries’ process roadmap is on track to intersect Intel’s at 14nm.

14nm will be the first process at which Intel intends to put mobile SOCs to the front of the node i.e. putting them among the first ICs to be made on a new process.

Asked if the foundries were prepping their next generation processes with the intention of putting mobile SOC at the front of the node, East replies: That’s the information we’re seeing from our foundry partners.”

Globalfoundries intends to have 14nm finfet in volume manufacturing in 2014, the same timescale as Intel has for introducing 14nm finfet manufacturing.

In fact, GF’s 14nm process may have smaller features than Intel’s 14nm process because, says Mojy Chian senior vp at Globalfoundries, because “Intel’s terminology doesn’t typically correlate with the terminology used by the foundry industry. For instance Intel’s 22nm in terms of the back-end metallisation is similar to the foundry industry’s 28nm. The design rules and pitch for Intel’s 22nm are very similar to those for foundries’ 28nm processes.”

Jean-Marc Chery, CTO of STMicroelectronics points out that the drawn gate length on Intel’s ˜22nm” process is actually 26nm.

Furthermore Intel’s triangular fins, which degrade the advantages of finfet processing could underperform GF’s rectangular fins which optimise the finfet advantage.

At the front of the GF 14nm finfet node will be mobile SOCs says Chian. GF has been working with ARM since 2009 to optimise its processes for ARM-based SOCs.

At TSMC the first tape-out on its 16nm finfet process is expected at the end of next year. That test chip will be based on ARM’s 64-bit V8 processor.

Using an ARM processor to validate its 16-nm finfet process should give TSMC’s ARM-based SOC customers great confidence.

Asked about the effects of finfets on ARM-based SOCs, East replies: “There’s no rocket science in what you get out of it. The question is does it deliver the benefits at an acceptable cost? You don’t get something for nothing. How much does it cost to manufacture? How good is the yield? And that, of course, affects cost.”

And so on goes Intel beating its head against the wall to get into the low-margin mobile business.

Recently Intel  said it expected its Q4 gross margin to drop 6% from Q3’s 63% to 57%. Shock, horror said the analysts

But if Intel succeeds in the mobile business, its gross margin will drop a lot more than that.

It’s a funny old world.

The Truth About Intel [Mannerisms on Electronics Weekly, Dec 5, 2012]

The darndest things are being said about Intel. The departure of its CEO is unexplained though I heard one person say it was voluntary.

Some people think Apple will put x86 in the iPad.

Others think Apple will drop x86 from iMacs so as to unify its processors across Phone, Pad and Mac.

Sure as eggs are eggs, both can’t happen

Some think Intel is going to become a foundry in a major way starting with Apple’s business – though it’s said the production cost of an Intel wafer is 3x that of a TSMC wafer.

Others say Intel may make wafers for a few customers but will not enter an industry servicing thousands of customers with hundreds of thousands of mask-sets.

Intel is to borrow $6 billion to buy its own shares something it has been doing for some time. I am too financially unsophisticated to understand why it does this but, even before this latest borrowing, Intel’s debt was already pretty high at over $7 billion and its cash rather low – for a cash generative, capex-gobbling company – at $10.5 billion.

The divi is generous – but the purpose of the generosity is to keep the share price up, then generosity hasn’t worked – Intel’s share price is under $20, unchanged in a decade.

The strategy of getting x86 into mobile phones seems mistimed when Apple and Samsung and now LG are designing their own mobile phone processors. This morning Samsung said it will start mass-roducing its own-brand 28nm processors for mobile devices early in 2013.

Intel’s fab situation at 22nm looks tough with 50% utilisation. A $500 million charge for this is expected to be taken in Q4.

Intel’s claim to have a manufacturing advantage looks unconvincing when its 22nm process turns out to have a drawn gate length of 26nm – virtually the same as volume processes at  leading foundries.

Where it matters, i.e. in the mobile market, Intel has no process advantage at all because Intel hasn’t yet put its mobile SOCs on its latest process at the start of a node. Intel’s mobile SOCs won’t enjoy early access to a new process node until the 14nm generation.

And was finfet the right bet?  20nm planar may still be made to work, while FD-SOI could turn out to be a better route than finfet. 

Meanwhile CEO Paul Otellini won the 2012 Open-Mouth-Insert-Foot Award by some spectacular boo-boos:

• Saying Windows 8 wasn’t ready just before its launch, provoked Microsoft’s riposte that Intel’s power management software wasn’t ready for the launch of Surface, Microsoft’s Windows 8 tablet.
• And endorsing Governor Mitt Romney in the recent US presidential elections probably irked the White House just as Otellini was earning some brownie points by sitting on a Presidential committee. They were much needed brownie points after Intel’s pasting from the FTC for ‘stifling innovation.’

And all the while and worst of all, the PC industry starts to contract and Intel has won few slots in the successor to the PC industry – the mobile device industry.

All in all a pretty rotten year for Intel despite taking in over $50 million in revenues and earning over $12 billion in profits.

Even silver linings can have clouds.

So the war is on as per: IBM, Intel face off at 22 nm [EE Times, Dec 10, 2012]

SAN FRANCISCO – Intel and IBM went head-to-head with their latest 22-nm technologies in back-to-back papers at the International Electron Devices Meeting (IEDM) here Monday (Dec. 10). Separately, a top Intel fab executive commented on increasing wafer costs and the company’s foundry business.

IBM said it is prototyping server processors in a new 3-D ready, 22-nm process technology it hopes will deliver 25 to 35 percent boosts over its 32-nm node. Intel retains an edge with several 22-nm chips already in volume production, and disclosure at IEDM of a variant of the process for SoCs for a wide range of applications.

The Intel paper showed support for “high drive current across the spectrum of leakage and a full suite of SoC tools,” Mark Bohr, head of Intel’s process technology development group, said in a brief interview. The process is geared for a much wider array of designs than that of IBM, he added.

Bohr said Intel’s 22-nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC’s 28-nm planar process. The addition of FinFET adds only 3 percent to the cost of the process. Its use of 80-nm minimum feature sizes can be made with a single pass of 193-nm lithography tools, making it cost effective.

Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said.

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.

Separately, Bohr said Intel does have a growing foundry business that may include some higher volume applications than its current announced customers like FPGA startup Achronix. However, “we don’t intend to be in the general-purpose foundry business…[and] I don’t think the [foundry] volumes ever will be huge” for Intel, he said.

Intel’s paper laid out characteristics of Intel’s 22-nm process variation for SoCs (see chart below). It outperforms Intel’s 32-nm planar process by 20 to 65 percent and covers four orders of magnitude in leakage current, said co-author C.H. Jan.

The process provides 51 to 56 percent improvements in high voltage performance used for fast interfaces such Ethernet, HDMI and PCI Express. That’s more than twice the 20 percent boost typical in this area for a new Intel node, Jan said.

In addition, analog performance went up three-fold after declines in the past three nodes. Intel offers a small library of analog circuits tailored to the process including precision resistors, metal-in-metal capacitors and high Q inductors.

The process supports high and standard performance options as well as low and ultra low power ones. It also includes SRAM designs optimized for density, power and performance some of which now hit 2.6 GHz at 1V, up from 1.8 GHz at 32 nm.

Finally, Intel created two new transistor designs specifically for the 22-nm SoC variant. One is focused on low power and the other on high voltage for mixed-signal and analog circuits (see chart above).

For its part, IBM described its 22-nm process using partially depleted silicon-on-insulator. IBM “has prototyped a number of server processors” in the node that achieve latency below 1.5 ns and 750 MHz random clock cycles, said IBM researcher S. Narasimha.

Narasimha declined to give specifics of what IBM might achieve with the 22-nm node. However he did say the goal was to provide 25 to 35 percent boosts of the previous node which delivered server processors running up to 5.5 GHz and others with up to 80 Mbytes embedded DRAM.

IBM created an SRAM cell that measures 0.026 mm² using the process. It also power supplies at 1.2V across a 550 mm2 die area, he said.

The process provides up to 15 levels of metal. The lowest five levels use 80-nm features, similar to the Intel process, and the top two levels support through-silicon vias for 3-D stacks with memory chips.

IBM will deliver a separate paper Wednesday on its 3-D stacking work.

Before that it was that Intel describes 22-nm SoC process, not chips [EE Times, Sept 13, 2012] 

Intel provided the first look at the system-on-chip variant of its 22-nm process technology in a talk at the Intel Developer Forum here Thursday (Sept. 13). However, it declined to provide details on the Atom-based SoCs for tablets and smartphones that will be made in that process.

“It’s fair to say Intel didn’t have much of a focus four or five years ago on SoCs, but that’s changed,” said Mark Bohr, director of Intel’s technology and manufacturing group in a process technology talk. “The success of Medfield [Intel’s 32-nm smartphone platform] shows we are learning to do it right, and I think we will have a technology advantage at 22 nm,” he said.

Intel showed at IDF six smartphones and four Windows 8 tablets using the Medfield SoC, made in an SoC variant of its 32-nm process. “There’s a lot more in the pipeline,” said Ticky Thakkar, a lead Atom designer in a separate talk on the mobile chips.

The company is already shipping to OEMs a 2-GHz version of Clover Trail, a follow on 32nm dual-core processor with boosted graphics. A 1.8-GHz version for tablets is also in the works.

Next up is Bay Trail, Intel’s first 22-nm SoC for tablets and smartphones, expected to debut at IDF Beijing [April 10-11, 2013 as per the IDF page of Intel]. “You’ll have to wait until next year to hear about it,” said Thakkar.

In a separate talk, Bohr described P1271, the 22-nm SoC process to be used for Bay Trail. It differs from the 22-nm CPU process now used for Intel’s Ivy Bridge processors by offering lower leakage logic transistors, higher voltage I/O transistors, denser upper layer interconnects and a set of precision resistors, capacitors and inductors.

“It’s not one set of features, but a menu of feature options—transistors, I/O, interconnects, passive elements and embedded memory,” Bohr said. “The [SoC] transistors go down to much lower leakage levels, but give up some performance,” he said.

The process has significantly better analog characteristics than Intel’s current 32-nm planar process. Designs make heavy use of 80-nm pitch features in lower metal layers, because they are the smallest features Intel can make at 22 nm without needing double patterning, he added.

Intel is running the process at three fabs, two in the U.S. and one in Israel. It will ramp soon in two other fabs.

Reminders: Silicon Technology for 32 nm and Beyond System-on-Chip Products [IDF 2009 presentation by Mark Bohr, Sept 23, 2009]

Products (Formerly Lincroft) [Intel page]
– Number of Products: 5
– Launch Range: Q2’11 – Q2’10
– Max TDP: 1.3W (Z600) – 3W (Z670)
– Z600 (512K Cache, 1.20 GHz) …
… Z670 (512K Cache, 1.50 GHz)

while the first SoC product was the Sodaville which had no real market success (even specs are not listed on the ark.intel.com), and as such was not continued:
– Intel Unveils 45nm System-on-Chip for Internet TV  [press release, Sept 24, 2009]

Intel Corporation today unveiled the Intel® Atom™ processor CE4100, the newest System-on-Chip (SoC) in a family of media processors designed to bring Internet content and services to digital TVs, DVD players and advanced set-top boxes.

The CE4100 processor, formerly codenamed “Sodaville,” is the first 45nm-manufactured consumer electronics (CE) SoC based on Intel architecture. It supports Internet and broadcast applications on one chip, and has the processing power and audio/video components necessary to run rich media applications such as 3-D graphics.

…

Intel® Atom™ Processor CE4100
The CE4100 processor can deliver speeds up to 1.2GHz while offering lower power and a small footprint to help decrease system costs. It is backward compatible with the Intel® Media Processor CE 3100 and features Intel® Precision View Technology, a display processing engine to support high-definition picture quality and Intel® Media Play Technology for seamless audio and video. It also supports hardware decode of up to two 1080p video streams and advanced 3-D graphics and audio standards. To provide OEMs flexibility in their product offerings, new features were added such as hardware decode for MPEG4 video that is ready for DivX* Home Theater 3.0 certification, an integrated NAND flash controller, support for both DDR2 and DDR3 memory and 512K L2 cache. The CE SoC contains a display processor, graphics processor, video display controller, transport processor, a dedicated security processor and general I/O including SATA-300 and USB 2.0.

Lincroft is mentioned in my Windows 7 tablets/slates with Oak Trail Atom SoC in December [Nov 1-24, 2010] post as:

Intel “is aiming to mass produce its Oak Trail platform for its Sleek Netbook segment targeting the tablet PC market in December 2010. The Oak Trail platform is a combination of Intel’s Lincroft (Atom Z6xx series) processor with Whitney Point chipset.”

…

The Oak Trail platform will sell at about US$25 with MeeGo [which was terminated as Nokia exited that joint effort 3 months later], and the price for Oak Trail and Microsoft’s Windows 7 will be higher.

so it was Intel’s first attempt to compete against the ARM-based tablet business, including the already successful iPad. As such it ended nowhere in terms of volumes. So adjustment followed as early as noted in my Intel: accelerated Atom SoC roadmap down to 22nm in 2 years and a “new netbook experience” for tablet/mobile PC market [April 17, 2012] despite that fact that products based on Z670 Atom from Lenovo and Fujitsu, as the big names, and Evolve, Motion Computing, Razer and Viliv, as much lesser names, appeared on the market from April, 2011 on (you could find information about them in the post itself). The price was too high: e.g. $729 for the Evolve III Maestro C.

The next Atom based on Intel’s 32nm SoC process appeared in fact just recently, first appeared in Acer Iconia W510: Windows 8 Clover Trail (Intel Z2760) hybrid tablets from OEMs [Oct 28, 2012] priced little lower, from $499 and up which is still overpriced relative to the ongoing 10” Android tablets. Moreover, it became available on in the second half of November and appeared on the Microsoft store to celebrate Cyber Monday (Nov 26) discounted to $399, which is the only competitive price. Now it is back to $499.

Lesson: Intel may speak about its “22 nm SoC process” but given the late entry of its 32nm SoC process Atom product (Cover Trail) it would be better to assume that with Windows 8 tablets based on that it will affect only the 2014 tablet market, not earlier. This is what the latest leaks are suggesting as well. Meanwhile expect a low-power Haswell ULT based tablet PC push in the H2 2013 as described already in my Intel Haswell: “Mobile computing is not limited to tiny, low-performing devices” [Nov 15 – Dec 11, 2012] post. As for the next year the real question is Can VIA Technologies save the mobile computing future of the x86 (x64) legacy platform? [this same blog of mine, Nov 23, 2012] For this watch what Allwinner vis-à-vis HTC on 2013 International CES [this same blog of mine, Dec 11, 2012] could bring in that respect, something much more than what is described in Allwinner A31 SoC is here with products and the A20 SoC is coming [USD 99 Allwinner blog of mine, Dec 10, 2012] or in $99 Android 4.0.3 7” IPS tablet with an Allwinner SoC capable of 2160p Quad HD and built-in HDMI–another inflection point, from China again [this same blog, Dec 3, 2012].

End of Reminders

FinFETs or FD-SOI? [SemiMD (Semiconductor Manufacturing and Design), Dec 11, 2012]

By Ed Sperling
STMicroelectronics yesterday unveiled the results of its 28nm production silicon chips using fully depleted silicon on insulator technology, which it claims offers a 30% improvement in speed over bulk CMOS while using less power.

The debate over FD-SOI and FinFETs has been notching up over the past few months. While FinFETs and FD-SOI both promise improvements in controlling leakage current, the FinFETs are more difficult to design. FD-SOI uses the same design flow, although it does use a different SPICE model with better characteristics than the one used for bulk CMOS.

ST also used an ultra thin body and box (UTBB) and body biasing to boost performance, according to Joel Hartmann, the company’s executive vice president of front-end manufacturing and process R&D. Hartmann presented his results at an SOI Consortium-sponsored event at the IEDM show last night.

“We are using body bias to boost performance,” Hartmann said. “You can do that with FD-SOI. We also decreased the Vdd of the device by applying body biasing.”

What’s particularly attractive about FD-SOI is that is can be implemented at the 28nm node for a boost in performance and a reduction in power. The mainstream process node right now is 40nm. And while Intel introduced its version of a finFET transistor called Tri-Gate at 22nm, TSMC and GlobalFoundries plan to introduce it at the next node—whether that’s 16nm or 14nm. That leaves companies facing a big decision about whether to move all the way to 16/14nm to reap the lower leakage of finFETs, whether to move to 20nm on bulk, or whether to stay longer at 28nm with FD-SOI.

Hartmann said ST has seen improvements in analog running on FD-SOI, and for memory where the minimum voltage required is lower. He said ST’s road map calls for FD-SOI all the way down to 10nm, with voltages dropping from 0.9v at 28nm to 0.8v at 14nm and 0.7v at 10nm.

One of the sticking points in adopting FD-SOI has been market acceptance. Despite the promise of improved performance and/or lower power, bulk CMOS has been extended using a variety of techniques such as strain engineering and FD-SOI is considered more expensive. At 28nm and beyond, however, bulk has run out of steam, which is why Intel has opted for finFETs.

Still, FinFETs are more difficult to design and manufacture, and they potentially can add significantly to the cost of an SoC. FD-SOI, in contrast, uses the same design tools and reduces the number of masks and metal layers. ST is the first large fab-lite company to adopt FD-SOI and to move beyond just test chips. It remains to be seen which path the rest of the industry takes—and how quickly.

Increasing Levels Of Risk [SperlingMediaGroup YouTube channel, Dec 11, 2012]

Inflection Points [SperlingMediaGroup YouTube channel, Aug 14, 2012]

See also: ST’s FD-SOI Tech Available to All Through GF [SemiMD (Semiconductor Manufacturing and Design), Oct 8, 2012]

– ARM Physical IP division via its upcoming IP is preparing with its foundry partners (TSMC, GLOBALFOUNDRIES and Samsung) an easier transition to FinFET

2012 ARM TechCon John Heinlein Interview [chipestimate YouTube channel, Dec 4, 2012]

TSMC OIP 2012 – Sit down with John Heinlein, ARM [chipestimate YouTube channel, Dec 4, 2012]

An introductory type video for the roundtable video which is the next:
ARM 16/14nm FinFET Manufacturing Leadership [Charbax YouTube channel, Nov 1, 2012]

ARM TechCon 2012 Executive Roundtable: Manufacturing [ARMflix YouTube channel, Nov 14, 2012]

Embedded in the beginning of this roundtable video there is a [4:19] minutes long Investing in FinFET Technology Leadership Presented by ARM [ARMflix YouTube channel, Nov 12, 2012] video in which Dr. Rob Aitken, R&D Fellow at ARM, discusses the need for new transistor technologies and how FinFET may be a solution. The embedded video is starting at [00:39] of the roundtable video. From this I will transcribe here the following part showing ARM’s commitment and strategy for FinFET in its Physical IP Division:

[02:30] ARM is taking a leadership position in FinFET IP development to accelerate the availability of FinFET IP in ARM partnership. We are working closely with foundry partners to develop prototype FinFET physical IP early in the process lifecycle. Using this prototype physical IP ARM is currently developing two different FinFET test chips both taping out in Q3 2012. These efforts continue ARM’s commitment to early development of silicon testing to reduce risk and time to market. Through our early engagement and prototyping work we actively provide feedback to our foundry partners to assure that FinFET technology is well suited to the requirements of energy efficient SoCs. ARM is further contributing to the technical community by publicly releasing fully pre-authorized FinFET transistor model based RTRs roadmap and is extending these models to more advanced FinFET designs. Internally we are modeling proprietary foundry technologies in support of the development work on those processes. This is just the beginning of ARM’s commitment to FinFET IP leadership. [03:46]

There are a number of other ARM specific information about its FinFET efforts in the September 27 report which is in the following major section. Now additional ones from its foundry partners:

Breathing New Life into the Foundry-Fabless Business Model [ARM’s SoC Design blog, Aug 21, 2012]

Early last week, GLOBALFOUNDRIES jointly announcedwith ARM another important milestone in our longstanding collaboration to deliver optimized SoC solutions for ARM® processor designs on GLOBALFOUNDRIES’ leading-edge process technology. We’re extending the agreement to include our 20nm planar offering, next-generation 3D FinFET transistor technology, and ARM’s Mali™ GPUs.
Our collaboration with ARM goes back many years, and its evolution parallels some of the critical developments in the larger semiconductor industry during the same timeframe. ….

…

This early and deep collaboration has resulted in several significant milestones, including the world’s first foundry optimized Cortex-A9 processor, POP™ IP for the Cortex-A9 processor operating at 1.6GHzon our 28nm-SLP technology, and a demonstration of more than 2GHzon our 28nm high-performance technology. This platform builds on the existing ARM Artisan® physical IP platforms for GLOBALFOUNDRIES processes at 65nm, 55nm and 28nm.

Now we are extending this collaboration to include true joint optimization for 20nm technologies and beyond, as well as a new focus on GPUs, which are becoming increasingly important in today’s smart mobile devices. The TQV strategy has already been scaled to 20nm and is an integral part of our process development, with a 20nm test chip implementation currently running through our Fab 8 in Saratoga County, N.Y.

And while we are seeing great dividends from this collaboration, the real hard work is only just beginning. We are now leveraging historical synergies from 28nm and 20nm planar technology to enable a smooth migration to next-generation, three-dimensional FinFET technology. One of the well publicized benefits of FinFET technology is its superior low-power attributes. The intrinsic capability of the 3D transistor to operate at a lower Vdd translates to longer battery life, which is heavily sought after in performance-hungry mobile computing applications. Our collaboration is focused tightly on this sweet spot in the market, where designers are looking for the optimum combination of performance, power-consumption, area, and cost. Our co-development work with ARM will enable a faster time to FinFET SoC solutions for customers using ARM’s next generation of mobile SoC IP for both CPUs and GPUs.

So clearly the foundry-fabless business model is not collapsing, but rather adapting to meet the challenges of today. Success will be a result of much closer joint development at the technology definition level, early engagement at the architectural stage, and a more integrated and cooperative ecosystem – precisely the kind of collaboration that we’re demonstrating with our valued partner ARM.

Guest Partner Blogger:

Mike Noonen is Executive Vice President, Worldwide Marketing and Sales, for GLOBALFOUNDRIES. In this role, he is responsible for global customer relationships as well as all marketing, sales, customer engineering and quality functions.

GLOBALFOUNDRIES at ARM Techcon 2012 [Charbax YouTube channel, Oct 30, 2012]

If interested in the GLOBALFOUNDRIES Fireside Chat mentioned here watch the separate video GLOBALFOUNDRIES Fireside Chat at ARM Techcon 2012 [Charbax YouTube channel, Oct 31, 2012] with the following content:

“The insatiable need for functional and feature integration on to Mobile SoCs, coupled with ever increasing performance demands has challenged the Foundries and Fabless Semiconductor companies alike. While the diminishing geometries of the process technologies have kept pace to address this challenge, the solutions for leakage power dissipation continued to fall behind threatening to thwart the advances in Mobility. The ground-breaking FinFET technology is the right low-power solution and will serve as an inflection point to further enable SoC-level integration and technological advances in this exciting era of Extreme Mobility. The panel will discuss how the next generation of FinFET technology will change the mobile revolution again.”

Speakers

Dean Freeman, Research VP, Gartner Research
Bruce Kleinman, VP, Product Marketing, GLOBALFOUNDRIES
Subramani Kengeri, Vice President, Technology Architecture Office of the CTO, GLOBALFOUNDRIES
Srinivas Nori, Director. SOC Innovation, GLOBALFOUNDRIES
Dipesh Patel, Deputy General Manager of the Physical IP Division, ARM

TSMC’s information about collaboration with ARM in FinFET space was already included in the second major section (September 27 Report) beginning from ARM and TSMC Collaborate to Optimize Next-Generation 64-bit ARM Processors for FinFET Process Technology [ARM press release, July 23, 2012] part in the text. As an update to that I will include here:  TSMC Accelerates finFET Efforts [SemiMD (Semiconductor Manufacturing and Design), Oct 16, 2012]

In response to its foundry rivals, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has updated and accelerated its process roadmap. The world’s largest silicon foundry has accelerated its 16nm finFET efforts by one quarter and added a 10nm finFET technology to the roadmap.

TSMC also plans to take the “modular fin” approach for its 16nm finFET. It is also looking at 450mm fabs at the 10nm node, according to a TSMC executive, who also stressed that collaboration is a key to success. Customers must collaborate earlier in the design cycle and “at a new level,” said Mark Liu, executive vice president and co-chief operating officer at TSMC, during a keynote at the company’s Open Innovation Platform Ecosystem Forum in San Jose, Calif. on Tuesday (Oct. 16). “We need to align strategically.”

At present, TSMC is ramping up its 28nm process technology. The next process on the roadmap, dubbed CLN20, is a 20nm planar technology. The reference flow for CLN20 is ready and the process is due out in 2013.

[See: TSMC 20nm and CoWoS™ Design Infrastructure Ready [TSMC press release, Oct 9, 2012]

Then, as previously announced, TSMC will enter the finFET transistor era. The company’s initial finFET process, dubbed CLN16FF, is being targeted and branded for the 16nm node. TSMC’s 16nm finFET process is slated for risk production in November of 2013, Liu said. Risk production has been accelerated from February of 2014 to November of 2013.

In an interview after the keynote, Liu said TSMC will take a “modular fin” approach in finFETs. TSMC will marry a 16nm fin with a 20nm backend. “It has 20nm design rules,” he said.

TSMC will also implement a triple-patterning strategy for 16nm finFETs. The company is also keeping its options open. It is exploring 193nm immersion extensions, extreme ultraviolet (EUV) lithography and multi-beam. “At this point, we have both (193nm extensions and EUV) under development,” he said. “Maybe multi-beam will save the day.”

TSMC’s 16nm finFET design solutions, including the EDA tools and IP, will be ready by the first quarter of 2013.  “We have pulled in our design enablement solutions,” said Cliff Hou, senior vice president of TSMC, during a separate keynote at the event. The first version of the design solutions, dubbed V0.1, is slated for introduction in January. The second version, V1.0, is due out in October of 2013.

Meanwhile, during his keynote, Liu presented a slide that denoted CLN10FF, which is a second-generation finFET for the 10nm node.  TSMC’s 10nm finFET process is expected to move into risk production “close to the end of 2015,” he said.

Also at 10nm, TSMC is looking to enter the 450mm fab era. It is likely TSMC will have a 450mm fab or pilot line in the second phase of 10nm. “There are no show stoppers,” he said. “All of the equipment companies are developing 450mm.”

Other foundries have also accelerated their finFET roadmaps. For example, GlobalFoundries Inc. recently rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM. The 14nm-XM combines a 14nm-class fin with its 20nm back-end-of-line (BEOL) interconnect flow.

By taking the modular approach, the company has accelerated its process roadmap by a year. Early process design kits (PDKs) are available, with customer product tape-outs expected in 2013. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.

Another foundry vendor, United Microelectronics Corp. (UMC), is taking a similar modular finFET approach. UMC licensed finFET technology from IBM. Samsung Electronics Co. Ltd. has yet to elaborate on its finFET strategy.  Meanwhile, Intel Corp. is already ramping up its 22nm process, which is based on finFET transistors. Intel is providing foundry services for select customers, who plan to ship products based on finFETs.

September 27 Report

In my role, I serve as one of the members of the Global

Semiconductor Alliance (GSA) Steering Committee on Intellectual Property, where we work to share best practices and continue to improve the IP ecosystem for the benefit of the entire semiconductor industry. As part of this role, I’ve observed a trend in the news speculating on the future of the foundry and IP industry, and I recently posted my thoughts on the GSA blog site, and I’d like to share them with you here as well.

In 1897, after a journalist erroneously reported the passing of famed author and humorist Mark Twain, Twain replied in his typical wit with the now famous retort: “the rumor of my death has been greatly exaggerated.”  Like the then very alive author, recent reports have speculated on the demise of the foundry and IP business model.  I similarly think such talk is pure nonsense.  Across many metrics the foundry and IP space is alive and well and providing unprecedented capabilities to semiconductor companies. [his factual argumentation for that you can find much below, in the <<sticking with the “Goliath”>> section]

Dr. John Heinlein, Vice President, Marketing, ARM Physical IP Division on May 16, 2012

– TSMC’s View of the Semiconductor IP Ecosystem 

To understand the semiconductor IP ecosystem one should first understand it via the IP related efforts of far the biggest and most influential foundry, TSMC (as their success most heavily depends on a vibrant and quality IP ecosystem):

ChipEstimate.com DAC 2012 IP Talks presenter Dan Kochpatcharin on TSMC OIP and IP Quality [chipestimate YouTube channel, June 26, 2012]

There are 41 IP partners in the semiconductor IP specific TSMC IP alliance program of TSMC OIP (Open Innovation Platform alliance ecosystem) and also have 20-25 IP partners directly supported but not part of the IP alliance program.

Among those the winners of the 2011 TSMC IP Partner Award of Year were:

• Interface IP: Synopsys Inc. [US]
• Analog/Mixed Signal IP: Dolphin Integration SA [France]
• Foundation IP [such as basic standard cells, standard I/O, and memory-bit cells]: ARM Ltd. [UK] [ARM Artisan® Physical IP such as: ARM® Artisan Standard Cell Libraries, ARM® Artisan Specialty I/O libraries, ARM® Artisan DDR Interface IP, ARM Artisan Embedded Memory Compilers etc. and Processor Optimization Packs (POPs)]
  
• Specialty Embedded Memory IP: eMemory Technology Inc. [Taiwan] for second year in a row

Note that for such an IP excellency the organisations behind are not big at all. Dolphin Integration SA is a 190 people company. eMemory employs around 200 people as per the award news release. While ARM Holdings Plc had 2,253 full-time employees alltogether at June 30, 2012, considering their Physical IP Division (PIPD) having just 11% of the overall revenue the number of employees there would probably not exceed 300. Artisan Components Inc. (US) acquired by ARM Holdings for not less than 1 billion US$ in Dec 2004 (because of “collaboration between the two companies on ARM’s next-generation MPU core, code-named “Tiger”, in 2005 becoming Cortex-A8) had 72 employees in 1997, so it is likely from historical point of view as well (considering even ARM’s heavy investment later on).

As far as Synopsys is concerned, 9 months ago it had ~6800 employees, but its portfolio is rather large (implementation, verification, IP, manufacturing and FPGA solutions), and in addition to the Interface IP the company has Analog IP and Memories and Logic Libraries as well in the overall DesignWare IP portolio. To understand that split let’s take the following “Top Interface, Analog, and Embedded Memory IP Vendor” presentation slide from Synopsis Investor Day 2011 presentation, referring to a Gartner, March 2011 report, which is indicating $104.1M interface IP revenue for 2010:
which is ~ 7.5% of the overall revenue of Synopsis (having $1.38B for the fiscal year 2010 ending Oct 31, 2010 when it had 6707 employees) which could mean ~500 employees related to Interface IP activities taken proportionally to the revenue.

And here are the number of titles in TSMC IP portfolio also vs. other foundries:

See also:
– TSMC Extends Open Innovation Platform™ [TSMC press release, June 7, 2010]
– TSMC Expands IP Alliance to Include Soft IP [TSMC press release, Oct 5, 2010]
– Atrenta and TSMC IP Quality Initiative Gains Broad Industry Acceptance [Atrenta press release, March 5, 2012]: “10 intellectual property (IP) providers have qualified their soft IP for inclusion in the TSMC 9000 IP library using the Atrenta IP Handoff Kit. Those companies, part of TSMC’s Soft-IP Alliance Program, include Arteris, Inc.; CEVA; Chips&Media, Inc.; Digital Media Professionals Inc. (DMP); Imagination Technologies; Intrinsic-ID; MIPS Technologies, Inc.; Sonics, Inc.; Tensilica, Inc.; and Vivante Corporation. The participating companies are able to provide quantitative information to TSMC’s customers regarding the robustness and completeness of their soft or synthesizable semiconductor IP that is part of the TSMC 9000 IP library.”
– Imagination Technology Forum: Advanced SoC solutions in cooperation with TSMC [detailed DIGITIMES report, June 28, 2012]: “Not only will we be introducing our latest graphics processing IP, we will also talk about video, displays, multi-threaded cores [Meta SoC Processors], and wireless processors [Ensigma Universal Communications Core Processors (UCCPs)]. We hope that industries can further understand that Imagination is a company that provides complete SoC solutions.“
– TSMC Open Innovation Platform® Ecosystem Forum, Technical Presentation Abstracts [TSMC, Oct 18, 2011]
– ARM Physical IP Overview [ARM presentation, Sept 9, 2011]
– Leveraging Advanced Physical IP to Deliver Optimized SoC Implementations at 40nm and below [ARM presentation, Nov 19, 2010] [Meta SoC Processors]
– ARM Announces Processor Optimization Pack [ARM press release, Nov 9, 2010]

ARM today announced the immediate availability of the ARM® Cortex™-A9 Processor Optimization Packs (“POPs”).  Processor Optimization Packs leverage ARM Artisan® physical IP to enable customers to achieve technology leading performance or power targets on their Cortex-A9 implementations in the shortest time to market. A silicon-proven POP is available now TSMC(R) 40nm G process technology.  The Cortex-A9 POP on TSMC 40nm LP process technology will be available to customers in January 2011.

The Cortex-A9 Processor Optimization Packages contain three elements: ARM Artisan optimized logic and memory physical IP for a specific process technology, supported by implementation knowledge and ARM benchmarking.  Combined together the POP allows SoC designers to optimize Cortex-A9 designs for maximum performance, lowest power or to develop customized solutions balancing power and performance for their specific application.

– Overall semiconductor IP market overview

The key players listed by the market researcher MarketsandMarkets (with ChipEstimate.com links wherever possible, where “Prime IP Partners” are highlighted in bold) are the following companies:

Notes:

1. ChipEstimate.com Chip Planning Portal Overview
   The ChipEstimate.com chip planning portal is an ecosystem comprised of over 200 of the world’s largest semiconductor design and verification IP suppliers and foundries. These companies all share in the common vision of helping the worldwide electronics design community achieve greater profitability and success. To date, a diverse global audience of over 27,000 users has joined the ChipEstimate.com community and has collectively performed over 100,000 chip estimations. ChipEstimate.com is a property of Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation.

2. Reasons for missing Coreworks S.A, Lattice Semiconductor, Mentor Graphics, Inc., MIPS, Inc., and MoSys, Inc. on the ChipEstimate.com portal are quite diverse. You can find them via the additional linked explanations, typically marked as “but see”.

Overall the summary of the Semiconductor Intellectual Property Market, Silicon IP Market (2012-2017): Global Forecasts & Analysis [MarketsandMarkets, April 2012] states that:

The growth trend of the Semiconductor IP market revenue can be observed by the CAGRs over various time periods. The CAGR of the Semiconductor IP market from 1997 to 2002 was 17.82% while the value from 2002 to 2007 stood at 11.54%. Post 2007, the market again picked up growth and the forecasted CAGR from 2012 to 2017 is estimated to be 14.47%. In 2012, the global Semiconductor IP market is estimated to be $2.90 billion. The percentage share of Semiconductor IP industry in the global revenue for semiconductors was approximately between 0.3% and 1.0% over the years; stood at 0.71% in 2011, and is estimated to increase to 0.85% by the end of 2012 and 0.99% by the end of 2017.

In the Analyst Briefing Presentation of the same report it is stated that:

Coming to the statistics, in 2011, the global Silicon IP Market stood at $2.25 billion, while the global semiconductor industry revenue was at $315 billion. Both these markets are estimated to reach $2.90 billion and $340 billion respectively by the end of 2012.

which means that while the global semiconductor industry is expected to grow just 6.3% this year the Semiconductor IP Market is estimated to grow by 28.9% ! So the latter is quite healthy although still a tiny part of the whole industry.

Gartner presented last year the following, revenue based Semiconductor IP Market view:
Source: Synopsis Investor Day 2011 presentation, referring to a Gartner, March 2011 report

Note that the $231.6M semiconductor IP revenue was just ~15% of the CY2010 overall revenue (~1.5B estimated at max) of Synopsis where Core EDA (Electronic Design Automation) was and is the bulk of the revenue by far: Core EDA revenue was $959M in FY2010 and $980.7M in FY2011. Relative to that the overall Semiconductor IP segment was and is a double digit growth area for Synopsis. Since the company is following a strong “M&A strategy to broaden TAM and provide incremental revenue growth” in non-Core EDA areas the semiconductor IP revenue will probably grow at the same pace in the coming years. Therefore its #2 position will be maintained on this market, especially as it has almost no competitors (only Mentor Graphics IP) among Top 10 (those companies having not less than 71.1% share of market), while the #3 Imagination Technologies’ strongest competitor is the #1 ARM Holdings, as well as the strongest competitor of the #4 MIPS Technologies is the same #1 ARM Holdings.

So overall the market is quite mature, with well established and strong leaders already having the most of the business for themselves. The #1 ARM Holdings is also having a strong ecosystem of its own, which is providing opportunities for not less than 53 small silicon IP vendors outside the Top 10 as well. See: SoC IP [providers in ARM Connected Community Program].

I’ve edited a more descriptive list of that in PDF, which you can download from here. Below I’am providing an excerpt from that, with strongest players in ARM’s own ecosystem in the sense of relying on ARM’s Artisan Physical IP via the IPNet Partner Program (denoted by +) and/or TSCM IP Alliance Program (denoted by *):

Analog Bits*: the leading supplier of low-power, customizable analog IP for easy and reliable integration into modern CMOS digital chips. Our product range includes precision clocking macros such as PLL’s & DLL’s, programmable interconnect solutions such as multi-protocol SERDES/PMA and programmable I/O’s as well as specialized memories such as high-speed SRAMs and T-CAMs.
– Low Power Wide Range PLL – Common Platform 32LP

Arteris*: Arteris invented Network on Chip technology, offering the world’s first commercial solution in 2006. Arteris connects the IP blocks in semiconductors from Qualcomm, Samsung, TI, and others, representing over 50 System on Chip devices. … Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech.
– C2C™ Chip to Chip Link™ Inter-chip Connectivity IP
– FlexNoC Network-on-Chip Interconnect IP
– FlexWay Interconnect IP

Aurora VLSI, Inc. +: provides AMBA specification-based SoC/ASIC IP components, peripherals, subsystems, and platforms. … Aurora provides a full set of popular communications and SoC IP cores for ARM and AMBA Bus-based SoCs.
– AMBA Peripherals- Ethernet, PCI, USB, IEEE1394, memory and flash controllers, interrupt controller, timers, counters, GPIOs, etc 
– AMBA SOC Platform (Configurable)

AuthenTec*: a leading provider of mobile and network security. … AuthenTec’s products and technologies provide security on hundreds of millions of devices, and the Company has shipped more than 100 million fingerprint sensors for integration in a wide range of portable electronics including over 15 million mobile phones. Top tier customers include Alcatel-Lucent, Cisco, Fujitsu, HBO, HP, Lenovo, LG, Motorola, Nokia, Orange, Samsung, Sky, and Texas Instruments.
– SafeXcel™ IP-06 KASUMI Crypto Core Family
– SafeXcel™ IP-115 HDCP2 Content Protection Crypto Module
– SafeXcel™ IP-123 Secure Platform Crypto Module
– SafeXcel™ IP-154 Public Key Infrastructure Cores
– SafeXcel™ IP-16 3DES Crypto Core Family
– SafeXcel™ IP-160 MACsec Security Engine w/ Classifiers
– SafeXcel™ IP-18 CAMELLIA Crypto Core Family
– SafeXcel™ IP-197 Inline Security Packet Engine
– SafeXcel™ IP-28: Public Key Accelerator Cores
– SafeXcel™ IP-3X AES Crypto Core Family
– SafeXcel™ IP-46 SNOW 3G Crypto Core Family
– SafeXcel™ IP-48 ZUC Crypto Core Family
– SafeXcel™ IP-57 HASH/HMAC Core Family
– SafeXcel™ IP-60 MACsec Frame Engine
– SafeXcel™ IP-62 MACsec/IPsec GCM Packet Engine
– SafeXcel™ IP-76 True Random Number Generator
– SafeXcel™ IP-97 Look-Aside Security Packet Engine

CEVA, Inc.*: the leading licensor of digital signal processor (DSP) cores, multimedia and storage platforms to leading semiconductor and electronics companies worldwide. … This portfolio includes a family of programmable DSP cores, DSP-based subsystems and application-specific platforms including multimedia, audio, Voice over Packet (VoP), Bluetooth, Serial ATA (SATA) and Serial Attached SCSI (SAS).
– Application Platforms: for Mobile Multimedia Applications
The Only Silicon-proven Programmable Solution Supporting H.264 codec up to D1 resolution! … Complete, Low-Cost Audio Solution … Complete, Single Processor VoIP Solution
– DSP Cores: The CEVA-X family of cores is based on CEVA’s latest pioneering DSP architecture. This architecture offers best-in-class performance, scalability, and lowest cost-of-development for DSP deployment … CEVA-TeakLite Architecture DSP core.
– System Platforms: Broad set of DSP peripherals extendible through APB … tailored for specific cores of the CEVA-X architecture framework … High performance multimedia platform … CEVA-TeakLite Architecture DSP subsystems

Chips&Media,Inc. *: video codec technologies cover the full line-up of video standards such as MPEG-2, MPEG-4, H.263, H.264/AVC and VC-1 from CIF to HD resolution.
– BODA7Series-HD Video Decoder IP
– BODA9Series-Dual HD Video Decoder IP
– CODA7Series-HD Video Codec IP
– CODA9Series-Dual HD Video Codec IP

Denali Software, Inc. +: Databahn™ products provide optimal control and data throughput for external DRAM (DDR2, DDR3, LPDDR1, LPDDR2) and Flash memory devices.
– Databahn NAND Flash Controller
– Databahn(TM) PCI Express Controller IP Core
– Databahn(TM) SDR/DDR1/DDR2/DDR3/LPDDR2 Solutions

eMemory Technology Inc. *: focused on the development of logic embedded non-volatile memory (NVM) such as OTP, MTP, and Flash. eMemory has published 186 patents. There are over 120 companies who have implemented our technologies and IP’s worldwide.
– NeoBit
– NeoFlash

Intrinsic-ID *: semiconductor IP and embedded software products based on Hardware Intrinsic Security. Our solutions revolve around patented Physically Unclonable Function (PUF) technology, where a secret key is extracted like a silicon biometric or fingerprint from silicon hardware directly and only when required.
Attackers have nothing to find because no key is stored nor present in the power down state. … Headquartered in Eindhoven, The Netherlands, Intrinsic-ID was founded in 2008 as a spin-out of Royal Philips Electronics and has been deployed in Philips’ production environment.
– AES
– HMAC-SHA-256
– iRNG
– Quiddikey™ in Hardware
– SHA-256

Kilopass *
– XPM: embedded, one-time programmable (OTP) non-volatile memory (NVM). … Over 70 customers have integrated XPM™ in over 200 designs from 180nm to 40nm. Applications range from a few hundred bits for unique ID to prevent cloning to multiple instances of 1Mb for program code storage.

PLDA, Inc. *: a leading provider of semiconductor intellectual property (IP) specialized in high-speed interconnect protocols and technologies.
– AMBA 2 AHB to PCI Bridge
– AMBA 2 AHB to PCI Express Bridge
– AMBA 2 AHB to USB 3.0 Device
– AMBA 2 AHB to USB 3.0 Host
– AMBA 3 AXI to PCI Express Bridge
– PCI Express IP Core with AXI interface

Rambus Inc. *: one of the world’s premier technology licensing companies specializing in the invention and design of high-speed memory architectures.
– XDR Memory: architecture … proven in high-volume, cost-competitive applications. Operating at 3.2Gbps, XDR DRAM provides 6.4GB/s of peak memory bandwidth with a single, 2-byte wide device.

Renesas Technology America, Inc. *
– Renesas Application Specific Products: SoC Architecture for Multimedia Controller Chip. Features: Multiple ARM 9 cores, Graphic Controller on chip, USB on chip, Memory Card Interface, Standard high-performance MCU peripherals, JTAG. Easy to customize with proven architecture and IP.

Sidense Corp. *: Sidense Corp. provides secure, dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes, with no additional masks or process steps required and no impact on product yield. Sidense’s patented one-transistor 1T-Fuse™ architecture  provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory IP solution and offers an alternative solution to Flash, mask ROM and eFuse in many applications.
– SiPROM
– SLP:
– ULP

Silicon Image GmbH *+
– Multimedia Platform IP: complete system solutions for Mobile Communication including MPEG-4 Encoding and Decoding for video chat and video conferencing applications. For Multimedia the offering incudes solutions for DVD Players and Set Top Boxes. Other leading edge technologies include a broad portfolio of security IPs and IP cores of professional networking applications.

Silicon Interfaces +
– Silicon Cores – Core to the Intelligent Systems(TM): 12+ IP cores targeted to areas such as Networking, Wireless, Communication and Interconnect, and around 5+ Verification IPs using Industry standard Verification Methodology

Sonics, Inc. *+:  a pioneer of network-on-chip (NoC) technology and today offers SoC designers the largest portfolio of intelligent, on-chip communications solutions.
– MemMax AMP: an intelligent Dynamic Random Access Memory scheduler designed for use with any AMBA AXI compliant bus fabric and memory controller.
– MemMax Scheduler: an intelligent Dynamic Random Access Memory scheduler designed for use with an OCP compliant memory controller.
– SonicsGN: Sonics’ 4th generation, configurable, on-chip network enabling the design of advanced SoC communications networks using a high-speed scalable fabric topology structure. As the industry’s highest frequency NoC available today, SGN allows SoC designers to deliver high-performance, simultaneous application processing for smart phones, mobile video and tablets.
– SonicsLX: On-chip Network contains a high performance advanced fabric with data flow services for the development of complex SoCs.
– SonicsMX: an actively decoupled, non-blocking, intelligent internal interconnect that enables designers to implement multiprocessor SoC architectures using combinations of similar or heterogeneous processing elements.
– SonicsSX: On-chip Network contains a high performance, advanced fabric and a comprehensive set of data flow services for the development of complex, multicore and multi-subsystem SoCs.

Synopsys *+:  world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. … Synopsys is headquartered in Mountain View, California, and has more than 70 offices located throughout North America, Europe, Japan, Asia and India.
– DesignWare Cores: Synopsys is a leading provider of high-quality, silicon-proven interface and analog IP solutions for system-on-chip designs. Synopsys’ broad IP portfolio delivers complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, Ethernet, HDMI and MIPI IP including 3G DigRF, CSI-2 and D-PHY. The analog IP family includes Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs, Video Analog Front-Ends, Touch Screen Controllers and more.
– DesignWare System-Level Library: a portfolio of tool-independent transaction-level models (TLMs) for the creation of virtual platforms. Virtual platforms are fully functional software models of complete embedded systems enabling pre-silicon software development and software-driven system validation.

As one could there 18 silicon IP vendors with very strong (Artisan and/or TSMC IP Alliance) ties in ARM’s own ecosystem, and out of them 5 (AuthenTec, CEVA, Rambus, Silicon Image and Syopsys) are in the Top 10 group of providers.

With that we could finish the overall semiconductor IP market overview.

– The CEVA case

A lot of Silicon IP vendors are highly focussed. Probably the most successful among them is CEVA Inc. (Israel, Choice IP Partner):

CEVA DSP – Company Introduction [cevadsp YouTube channel, Aug 4, 2011]

CEVA, Inc. Announces Second Quarter 2012 Financial Results [CEVA press release, July 31, 2012]

… Total revenue for the second quarter of 2012 was $13.6 million, a decrease of 6% compared to $14.4 million for the second quarter of 2011. Licensing revenue for the second quarter of 2012 was $5.4 million, an increase of 3% compared to $5.2 million reported for the second quarter of 2011. Royalty revenue for the second quarter of 2012 was $7.6 million, compared to $8.3 million reported for the second quarter of 2011. Revenue from services for the second quarter of 2012 was $0.6 million, compared to $0.9 million reported for the second quarter of 2011.

Gideon Wertheizer, Chief Executive Officer, stated: “The second quarter was the strongest licensing quarter in more than three and a half years, driven by a strategic licensing agreement with a tier 1 handset OEM for a range of LTE handsets and the first agreement for our newest DSP, the CEVA-XC4000 for LTE- Advanced. These latest agreements bring the total LTE design wins for CEVA DSPs to date to more than 20, and form the foundation for future royalty growth. Finally, while the competitive 2G market is experiencing pricing pressure, our volume growth in the lucrative 3G market during the quarter significantly outpaced that of the overall 3G space, as low and mid-range 3G smartphones gain traction.” …

About CEVA, Inc.

CEVA is the world’s leading licensor of silicon intellectual property (SIP) DSP cores and platform solutions for the mobile, portable and consumer electronics markets. CEVA’s IP portfolio includes comprehensive technologies for cellular baseband (2G / 3G / 4G), multimedia (HD video, Image Signal Processing (ISP) and HD audio), voice over packet (VoP), Bluetooth, Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2011, CEVA’s IP was shipped in over 1 billion devices and powers handsets from every top handset OEM, including HTC, Huawei, LG, Motorola, Nokia, Samsung, Sony and ZTE. Today, more than 40% of handsets shipped worldwide are powered by a CEVA DSP core. For more information, visit www.ceva-dsp.com. Follow CEVA on twitter at www.twitter.com/cevadsp.

LTE-A Ref.Architecture [part of the Ceva-XC4000 product page, Feb 20, 2012]

CEVA-XC4000 multi-mode LTE-Advanced reference architecture

Based on multiple CEVA-XC4000 processors, CEVA offers a complete multimode LTE-Advanced reference architecture targeting LTE-A Rel-10 Cat-7. The reference architecture was developed together with mimoOn, a member of the CEVA-XCnet partner program and addresses the entire PHY layer requirements.

Reference architecture highlights:

• A complete LTE PHY system architecture addressing the entire PHY layer requirements of multiple standards in software including: TD-LTE-A, HSPA+ Rel-9, TD-SCDMA, WiMAX and more

• Built around CEVA-XC4000 processors with minimal complementary hardware accelerators

• Offers industry’s most competitive SDR platform in terms of both cost and power consumption

• Supports maximal throughput of LTE-A Rel-10 CAT-7 UE FDD (DL: 300Mbps, UL: 100Mbps) with up to 8×4 MIMO and carrier aggregation of up to two carrier components to a total of 40MHz channel

• High operating margins enabling customer differentiation by software

[See also the related press release, as well as the  CEVA Continues to Dominate DSP IP Market with 90% Market Share [May 14, 2012] press release]

CEVA is also a best case for the trend determining the future of the semiconductor IP ecosystem, especially with the above “small print” example of a reusable LTE Advanced subsystem. More about the formation of such a trend you can find in the <<sticking with the “Goliath”>> section below.

– When sticking with the “Goliath”: ARM Holdings Plc

Then there are a number of vendors with an ecosystem of surrounding IP partners such as ARM Holdings Plc on the higher end (which we’ve already presented in the earlier, “Market Overview” section) and CAST Inc. on the lower one.

Let’s examine the future of the semiconductor IP ecosystem through the eyes of these two companies. What they can offer strategically to their customers? Why customers are selecting the smaller and much less influential offerings from CAST against the “industry behemoth” ARM? What does it mean for a customer sticking with one against the other?

Making IP work and getting the right SoC! [Global Semiconductor Alliance (GSA) Intellectual Property blog, July 18, 2012]

Jack Browne, Vice President, Marketing, Sonics, Inc.

Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience. Whether for pacesetting smart phones, WiFi routers, or personal medical devices, making all this IP work as intended in the SoC requires system IP.  System IP includes the on-chip network, performance analysis tools, debug tools, power management and memory subsystems necessary for best in class SoCs. Whether used by the architect in the initial definition of the SoC or the layout engineer finalizing timing for place and route closure, system IP is critical to the design insuring that the capabilities of the SoC will meet the required end user experiences.

…

For complex SoCs over 100 IP blocks may be included in a design.  Choices can be tough, with over a hundred IP vendors offering solutions, each with multiple products.  The System IP eases the design burden by supporting both IP blocks and subsystems with the necessary broad range of interface protocols, widths, frequency domains and power domains.

System IP eases the challenges of maintaining a common software platform over multiple generations of SoC’s, built with varying IP cores and subsystems. Market research firm Semico, forecasts subsystem functions for computing, memory, video, communications, multimedia, security and system resource management. The increased abstraction from subsystems gives productivity benefit (leveraging use of commercial IP blocks) as well as differentiation through the integration of in-house IP blocks with standard industry IP blocks into reusable subsystems. A computing subsystem example would be ARM’s big.LITTLE CPU clusters where ARM does most of the integration ahead of time with the designer doing final configuration of features and/or number of cores.  Another example would be faster communication subsystems like LTE advanced subsystems [we have already shown CEVA’s LTE-A Ref.Architecture above as the best example for that]. By customizing a 4G LTE advanced subsystem solution with internal technology, SoC design teams can differentiate from standard IP blocks using their internal expertise while leveraging the shared R&D benefits of merchant 4G IP subsystems.

With the increasing cost of today’s SoCs, many are designed for multiple markets where not all of the functionality of the SoC is in use.  Many also have multiple usage scenarios within a given market, e.g. music playback on our smartphone. With the importance of battery life, managing the power of a SoC, including the ability to power off unused blocks, gives the best battery life.  Today’s 28nm SoCs are using dozens of power domains and even more clock domains to meet the performance and battery life requirements. By moving to system IP supporting hardware centric control of power transitions, end users will make more use of Dark Silicon (normally powered off) for better battery life as compared to interrupt centric software power management control.

When starting a new SoC design, your choice of system IP is a key early decision as you have now selected the on-chip network, performance analysis tools, debug tools, power management and memory subsystems available for your design.  Making the right choice can provide a 2x benefit over other choices with regard to performance, power and cost, so make an informed choice.

Foundry and IP Business Model: Alive and Well [Global Semiconductor Alliance (GSA) Intellectual Property blog, May 16, 2012]

Dr. John Heinlein, Vice President, Marketing, ARM Physical IP Division

… The IP ecosystem … is diverse and vibrant, with today’s IP providers offering many IP types, spanning a wide range of power, performance and area tradeoffs.  As an example, at 45 and 40nm various industry databases list between 450-620 licensable IP blocks available.  Furthermore, the latest IP developments at 45nm and 28nm include extensive power management capabilities, cost tradeoffs and implementation options that give designers choices for their chip.  Only through this ecosystem diversity can we have the rich and competitive landscape to address the many market segments the industry serves.

… Major technology investments are occurring across the foundry space, with new leading-edge R&D investments in fundamental process technology being made.  These investments span major companies like IBM, TSMC, Samsung, GLOBALFOUNDRIES, research consortia like IMEC and even new entrants like SuVolta, all of which are driving for aggressive technologies.  Today, 32 and 28nm products are in production and many more ramping to production.  Following that, there is a range of solutions already announced at 20nm that deliver the next node of planar bulk CMOS scaling.  Furthermore, the industry has clearly shown its commitment to investing in the next wave of 20nm and 14nm solutions beyond bulk ranging from FinFET to fully depleted SOI. …

Clean Sweep at 28nm for ARM Artisan Physical IP [GSA Intellectual Property blog, Oct 11, 2011]

John A. Ford, Director of Product Marketing, Physical IP Division, ARM

On October 6^th, UMC announced the selection of the ARM® Artisan® Physical IP Platform for the UMC foundry sponsored IP program. This new platform for UMC’s 28nm high-K metal gate (HKMG) process is a natural continuation of the long standing relationship between ARM physical IP division and UMC. ARM Artisan IP has been successfully used in millions of SoCs produced at UMC for more than 10 years on 180nm, 130nm, 90nm, 65nm and 55nm process technologies. The addition of UMC to ARM’s family of 28nm Physical IP platforms has a larger meaning than just a high quality set of IP on a technology-leading process. ARM Artisan IP is now the only physical IP platform available at all four of the 28nm commercial foundries in the world: TSMC, UMC, GLOBALFOUNDRIES, and Samsung.

This makes good sense considering ARM’s expertise in physical IP optimization and years of establishing early foundry engagement on advance node IP development. ARM started work on physical IP for HKMG processes way back in 2008 with test chips and process qualification chips for IBM’s 32nmLP process. 32nmLP process was the first commercially available HKMG process and is now in high volume production at Samsung for smart phone, tablet and other applications. With millions of production SoCs at 32nm, 28nm is actually the 2^nd generation of HKMG IP from ARM and includes all the critical design technique learning from 32nm development and production. ARM is deploying a full platform of standard cells, logic products, memory compilers and interface products at 28nm. Customers can benefit from being able to use consistent IP at all four foundries for the development of their SoC. With ARM’s exhaustive silicon validation process, customers have the assurance, peace of mind and confidence that only comes for using ARM IP.

We’re not stopping there. ARM is now actively developing 20nm physical IP at both IBM and TSMC, with 5 test chips taped out starting in 2009 and several more planned for 2012 and 2013. By engaging early with foundries and developing IP in parallel with the process development, ARM ensures that designers can achieve the full entitlement of the technology, with a high degree of manufacturability. Foundries engage with ARM as a partner for early physical IP because of the long experience we have in developing physical IP on advanced process including CMOS SiON, CMOS HKMG and SOI. …

ARM big LITTLE processing: Saving Power through heterogeneous multiprocessing and task content migration [chipestimate YouTube channel, June 18, 2012]

From: Enabling Mobile Innovation with the Cortex™-A7 Processor [ARM whitepaper for TechCon 2011 by Brian Jeff, Oct 15 2011]

Market requirements for high-end mobile

High-end smartphones require high performance applications processors and graphics processors, but instantaneous performance requirements are highly elastic. During web browsing, for example, peak performance is required when pages are first rendered, but much lower levels of processor performance are required when reading or scrolling down a page. Similarly, applications have varying levels of performance requirements, typically requiring very high performance during launch, and low to moderate levels of required performance during at least some portion of runtime. For voice calls, the level of performance required by the applications processor is quite low, even on a high-end smartphone.

Given the wide range of required performance, it would be ideal if the phone could use a very power efficient CPU some of the time, and migrate the context to a high performance CPU at other times. ARM has been researching this idea for several years, and has specifically designed the Cortex-A7 CPU not only to ideally fit all but the high-end performance requirements of a high-end smartphone, but also to be able to connect tightly with the larger and higher performance Cortex-A15 CPU in a coherent system. When connected together through AMBA Coherency Extension (ACE) interface a Cortex-A15 CPU cluster can be connected with a cluster of Cortex-A7 CPUs in a processor complex with a single memory map, hardware managed cache coherency, and the ability to run workloads on the large CPU cluster or small CPU cluster depending on instantaneous performance requirements. This concept created by ARM is called big.LITTLE processing.

big.LITTLE Processing

Big.LITTLE refers to the coherent combination of High Performance and Power Efficient ARM CPUs A platform that contains both Cortex-A15 (big) and Cortex-A7 (LITTLE) can execute across a wider performance range with better energy efficiency than a single processor. Hardware coherency between Cortex-A15 and Cortex-A7 enables distinct big.LITTLE use models, either migrating context between the big and little clusters, or OS aware thread allocation to the appropriately sized CPU or CPUs. The CCI-400 cache coherent interconnect enables an extremely fast context migration between the big and little CPU clusters. Finally, software views the big and LITTLE CPU clusters identically, and transitions are managed automatically by OS power management or directly by the OS. The Net result of big.LITTLE power management is a platform with the peak performance of the Cortex-A15, and average power consumption closer to the Cortex-A7. This enables significantly higher performance at lower power than today’s high-end smartphones. The concept of big.LITTLE processing is only briefly introduced here; a more complete description of the ardware, software, and system implementation of big.LITTLE processing is covered in other TechCon resentations.

From: Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7 [ARM whitepaper by Peter Greenhalgh, Sept 15 2011]

In general, there is a different ethos taken in the Cortex-A15 micro-architecture than with the Cortex-A7 micro-architecture.  When appropriate, Cortex-A15 trades off energy efficiency for performance, while Cortex-A7 will trade off performance for energy efficiency.  A good example of these micro-architectural trade-offs is in the level-2 cache design.  While a more area optimized approach would have been to share a single level-2 cache between Cortex-A15 and Cortex-A7 this part of the design can benefit from optimizations in favor of energy efficiency or performance.  As such Cortex-A15 and Cortex-A7 have integrated level-2 caches.

Table 1 illustrates the difference in performance and energy between Cortex-A15 and Cortex-A7 across a variety of benchmarks and micro-benchmarks.  The first column describes the uplift in performance from Cortex-A7 to Cortex-A15, while the second column considers both the performance and power difference to show the improvement in energy efficiency from Cortex-A15 to Cortex-A7.  All measurements are on complete, frequency optimized layouts of Cortex-A15 and Cortex-A7 using the same cell and RAM libraries. All code that is executed on Cortex-A7 is compiled for Cortex-A15.

	Cortex-A15 vs Cortex-A7 Performance	Cortex-A7 vs Cortex-A15 Energy Efficiency
Dhrystone	1.9x	3.5x
FDCT	2.3x	3.8x
IMDCT	3.0x	3.0x
MemCopy L1	1.9x	2.3x
MemCopy L2	1.9x	3.4x

Table 1 Cortex-A15 & Cortex-A7 Performance & Energy Comparison

It should be observed from Table 1 that although Cortex-A7 is labeled the “LITTLE” processor its performance potential is considerable.  In fact, due to micro-architecture advances Cortex-A7 provides higher performance than current Cortex-A8 based implementations for a fraction of the power.  As such a significant amount of processing can remain on Cortex-A7 without resorting to Cortex-A15.

…

big.LITTLE Task Migration Use Model

In the big.LITTLE task migration use model the OS and applications only ever execute on Cortex-A15 or Cortex-A7 and never both processors at the same time.  This use-model is a natural extension to the Dynamic Voltage and Frequency Scaling (DVFS), operating points provided by current mobile platforms with a single application processor to allow the OS to match the performance of the platform to the performance required by the application.

However, in a Cortex-A15-Cortex-A7 platform these operating points are applied both to Cortex-A15 and Cortex-A7.  When Cortex-A7 is executing the OS can tune the operating points as it would for an existing platform with a single applications processor.  Once Cortex-A7 is at its highest operating point if more performance is required a task migration can be invoked that picks up the OS and applications and moves them to Cortex-A15.

This allows low and medium intensity applications to be executed on Cortex-A7 with better energy efficiency than Cortex-A15 can achieve while the high intensity applications that characterize today’s smartphones can execute on Cortex-A15.

An important consideration of a big.LITTLE system is the time it takes to migrate a task between the Cortex-A15 cluster and the Cortex-A7 cluster.  If it takes too long then it may become noticeable to the operating system and the system power may outweigh the benefit of task migration for some time.  Therefore, the Cortex-A15-Cortex-A7 system is designed to migrate in less than 20,000-cycles, or 20-microSeconds with processors operating at 1GHz.

big.LITTLE MP Use Model

Since a big.LITTLE system containing Cortex-A15 and Cortex-A7 is fully coherent through CCI-400 another logical use-model is to allow both Cortex-A15 and Cortex-A7 to be powered on and simultaneously executing code.  This is termed big.LITTLE MP, which is essentially Heterogeneous MultiProcessing.  Note that in this use model Cortex-A15 only needs to be powered on and simultaneously executing next to Cortex-A7 if there are threads that need that level of processing performance.  If not, only Cortex-A7 needs to be powered on.

big.LITTLE MP is compelling because it enables threads to be executed on the processing resource that is most appropriate.  Compute intensive threads that require significant amounts of processing performance, as their output is user visible, can be allocated to Cortex-A15.  Threads that are I/O heavy or that do not produce a result that is time critical to the user can be executed on Cortex-A7.

A simple example of a non-time critical thread is one associated with e-mail updates.  While web browsing the user will want email updates to continue, but it does not matter if they are done at CortexA15 performance levels or Cortex-A7 performance levels.  Since Cortex-A7 is a more energy efficient processor it makes more sense to take a LITTLE longer, but consume less battery life.

Finally, as a fully coherent system can create a significant volume of coherent transactions, Cortex-A15, Cortex-A7 and CCI-400 have been designed to cope with worst case snooping scenarios.  This includes the case where a Mali™-T604 GPU is connected to one of the I/O coherent CCI-400 ports and every transaction is snooping Cortex-A15 and Cortex-A7 at the same time as Cortex-A15 and Cortex-A7 are snooping each other.

From Combining large and small compute engines – ARM Cortex-A7 [by Brian Jeff on ARM SoC Design blog, Oct 19, 2011]

The fourth and final thing is to ensure these engines work with a regular transmission.

We needed to ensure there was a simple software approach to controlling the big.LITTLE switch consistent with power management mechanisms already in place. Current smartphones and tablet devices make use of Dynamic Voltage and Frequency Scaling (DVFS) and multiple idle modes for individual CPU cores and IP blocks in the application processor SoC. Our implementation of big.LITTLE modifies the back end of the driver which controls the processor’s DVFS operating point (for example cpu_freq in Linux/Android). Instead of three or four DVFS operating points, the driver now is aware of two CPU clusters each potentially with three or four independent voltage and frequency operating points, extending the range of performance tuning that existing smartphone power management solutions use. A big.LITTLE CPU cluster can be operated in a pure switching mode, where only one CPU cluster is active at a time under control of the DVFS driver, or a big.LITTLE heterogeneous multiprocessing mode where the OS is explicitly controlling the allocation of threads to the big or little CPU clusters and is thus aware of the presence of the different types of cores.

ARM Cortex-A7 launch — Intro Simon Segars, President ARM Inc [US] [ARMflix YouTube channel, Oct 19, 2011]

ARM Cortex-A7 launch — Presentation, Mike Inglis, EVP & GM ARM Processor Division [ARMflix YouTube channel, Oct 19, 2011]

Cortex-A7: Redefining Energy-Efficiency (DMIPS/mW)

• Most energy-efficient applications processor
  ƒ- 5x the energy efficiency of mainstream phones
  
• ƒPerformance to handle common workloads
  ƒ- >2x the performance of mainstream phone
  
• Feature set and software compliant with Cortex-A15
  ƒ- Full backward compatibility
  ƒ- Scalable and extensible
• Up to 20% more performance while consuming 60% less power

From: Enabling Mobile Innovation with the Cortex™-A7 Processor [ARM whitepaper for TechCon 2011 by Brian Jeff, Oct 15 2011]

The Cortex-A7 processor was designed primarily for power-efficiency and a small footprint. The design team based the pipeline on the extremely power efficient Cortex-A5 CPU, then added microarchitecture enhancements to increase performance and architectural enhancements to deliver full software compatibility with the Cortex-A15 CPU. These architectural enhancements include support for virtualization and 40-bit physical address space, and AMBA® 4 bus interfaces. Virtualization and large address space are unusual features for so small a CPU, but are critical to present a software view of the Cortex-A7 that is identical to the Cortex-A15 high-end CPU.

Like the Cortex-A5, Cortex-A9, and Cortex-A8 processors that came before it, the Cortex-A7 processor is a full ARM v7A CPU, with support for the Thumb®-2 instruction set, optional 32-bit/64-bit floating point acceleration and optional NEON™ 128-bit SIMD architectural blocks. The Cortex-A7 also includes support for TrustZone® to enable secure operating modes which are increasingly important in modern mobile OEM designs. To bring higher scalability, the Cortex-A7 is also configurable as a multicore processor, supporting 1-4 cores in a coherent cluster.

The Cortex-A7 is a simple in-order pipeline with significant but not complete dual-issue capability; however the careful choice of design features has enabled the performance of a single Cortex-A7 core to outperform the full dual-issue Cortex-A8 CPU on some important benchmark tests like web browsing, while consuming up to 60% less power.

…

Cortex-A7 Microarchitecture

The roadmap below shows the legacy of Cortex-A class CPU designs, beginning with the Cortex-A8. In that design, ARM introduces the NEON SIMD architectural extension, and implemented a 2-way superscalar CPU that brought significant performance enhancements over the single-issue ARM11™. The Cortex-A9 extended the Cortex-A8 by bringing in MPCore capability for 1 to 4 CPU’s with cache coherency managed efficiently by a snoop control unit. The Cortex-A9 also introduced performance enhancements inside the core that brought a 20-30% performance increase over Cortex-A8 for a single core.

Cortex-A7 makes use of a simple 8-stage in-order pipeline, extended to include dual-issue capability on a reduced range of data-processing and branch instructions. Increased dual-issuing coupled with other microarchitectural improvements allow the Cortex-A7 to reach very good levels of performance with very low power consumption.

Other performance enhancing features include an integrated L2 cache, which reduces latency to L2 memory and external memory. The integrated L2 cache simplifies OS support as it uses system mapped registers and can be managed using CP15 operations rather than the memory mapped registers needed for an external L2 cache. Integrating the L2 cache controller also reduces the amount of area consumed by an external controller and enables a tighter integration of the controller with internal bus structures.

The L2 cache controller itself was designed with low power in mind. The mechanism for looking up tags in the cache RAM includes consecutive tag followed by data lookup; similarly, the associativity is fixed at 8-way to balance performance against lookup energy. External requests are triggered on an L2 miss, rather than on speculative requests, to reduce energy.

There are branch prediction improvements as well: the branch target instruction cache (BTIC) caches fetches after a direct branch and hides the branch shadow on tight loops.

There are several improvements in memory system performance. The Load-Store path has been increased to 64-bits from the 32-bit path in the Cortex-A5. The external bus structure has been upgraded to 128-bit AMBA4 to improve bandwidth and introduce support for coherency extension beyond the 1-4 SMP cluster using AMBA 4 ACE.

Energy Efficiency Features of the Microarchitecture

There are several features of the L1 Memory system which reduce the power consumption of the CPU or the system. The merging Store-buffer after the write stage reduces data cache lookups. The 2-way set associative instruction cache trades off the slightly improved hit rate of a 4-way set associative cache for the reduced power on each lookup.

Memory System Tuned to Minimize memory latency

There are several performance optimizing features in the memory system. The address generation unit is shifted one stage back in the pipeline to enable a single cycle load-use penalty. The design team increased TLB size to 256 entries, up from 128 entries for the Cortex-A5 and Cortex-A9; this reduces page walks saving power and significantly improves performance for large workloads like web browsing with large data sets that span a large number of pages. Also, page tables entries can be cached in L1, improving the speed of page table walks on TLB misses. The bus interface unit has support for multiple outstanding read and write transactions. Finally, the physically indexed caches enable efficient OS Context switching.

ARM Cortex-A7 launch — big.LITTLE demonstration, Nandan Nayampally, Director, Product Marketing [ARMflix YouTube channel, Oct 19, 2011]

ARM Expands Processor Optimization Pack Solutions for TSMC 40nm and 28nm Process Variants [ARM press release, April 16, 2012]

…

A Processor Optimization Pack solution is composed of three elements necessary to achieve an optimized ARM core implementation. First, it contains ARM Artisan® Physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology.

This Physical IP is developed through a tightly coupled collaboration with ARM processor engineers in an iterative process to identify the optimal results. Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation. Finally, it includes a POP Implementation Guide that details the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.

“A single POP product can be applied to energy-efficient mobile, networking or even enterprise applications, providing a wide range of flexibility for ARM SoC partners to optimize performance and energy-efficiency while reducing risk in their designs,” said Simon Segars, executive vice president and general manager, Processor and Physical IP Division, ARM. “Only ARM can offer a complete roadmap of Processor Optimization Pack implementation solutions so deeply integrated and tightly aligned with ARM processor development activities now and into the future.”

The summary below describes the existing and newly announced POP products for TSMC processes. ARM also incorporates the POP optimizations in hard macros of Cortex cores.

POP availability by process technology

TSMC 40LP	TSMC 40 LP high speed options	TSMC 40 G	TSMC 28 HPM	TSMC 28 HP
ARM Cortex™-A5 Existing	Cortex-A5 New
Cortex-A7 New	Cortex-A7 New		Cortex-A7 New
Cortex-A9 Existing	Cortex-A9 New	Cortex-A9 Existing	Cortex-A9 New	Cortex-A9 New
			Cortex-A15 New	Cortex-A15 Upcoming

ARM Announces Cortex-A15 Quad-Core Hard Macro [ARM press release, April 17, 2012]

Power-optimized implementation of quad-core hard macro on leading 28nm process

ARM today announced the availability of a high performance, power-optimized quad-core hard macro implementation of its flagship ARM® Cortex™-A15 MPCore™ processor.  

The ARM Cortex-A15 MP4 hard macro is designed to run at 2GHz and delivers performance in excess of 20,000DMIPS, while maintaining the power efficiency of the Cortex-A9 hard macro. The Cortex-A15 hard macro development is the result of the unique synergy arising from the combination of ARM Cortex processor IP, Artisan® physical IP, CoreLink™ systems IP and ARM integration capabilities, and utilizes the TSMC 28HPM process.

The low leakage implementation, featuring integrated NEON™ SIMD technology and floating point (VFP), delivers an extremely competitive balance of performance and power and is ideal for wide array of high-performance computing applications for such as notebooks through to power-efficient, extreme performance-orientated network and enterprise devices. 

The hard macro was developed using ARM Artisan 12-track libraries and the recently announced Processor Optimization Pack™ (POP) solution for the Cortex-A15 on TSMC 28nm HPM process. This follows the recent announcement of a broad suite of POPs for all Cortex-A series processors (see ARM Expands Processor Optimization Pack Solutions for TSMC 40nm and 28nm Process Variants, 16th April 2012)

Full configuration and implementation details will be presented at the Cool Chips conference (18-20 April) in Yokohama, Japan. Further information is contained in an accompanying blog.

“For SoC designers looking to make a trade-off between the flexibility offered by the traditional RTL-based SoC development strategy and a rapid time to market, with ensured, benchmarked power, performance and area, an ARM hard macro implementation is an ideal, cost-effective solution,” said Jim Nicholas, vice president of Marketing, processor division, ARM. “This new Cortex-A15 hard macro is an important addition to our portfolio and will enable a wider array of partners to leverage the outstanding capabilities of the Cortex-A15 processor.”

See also:

– Squaring the circle – Optimizing power efficiency in a Cortex-A15 processor [Haydn Povey on SoC Design blog of ARM, April 17, 2012]
– Simplifying SoC’s with Hard Macros – New solutions for old problems [Haydn Povey on SoC Design blog of ARM, Oct 20, 2011]: “For me, the most important aspect of this talk was the public announcement of the availability of a new Cortex™-A5 Hard Macro for the TSMC 40nm Low Power node (40LP) which can achieve a whopping speed of over 1GHz in a tiny footprint of just 1mm². … there will always be partners who need the full flexibility of RTL and POPs, but there is also a group for whom having a pre-integrated and hardened ready to run solution out of the box is the best route to market.”
–  Hard Macro Processors [ARM product page, April 17, 2012]

The ARM Hard Macro portfolio offers performance and power optimized hard macrocell implementations of the Cortex™-A series processors. For SoC designers looking to make a trade-off between the multifaceted flexibility offered by the traditional RTL based SoC development strategy and the significant costs and efforts it involves, the ARM Hard Macro portfolio is an exciting alternative that enables higher profitability through benchmarked PPA (Performance, Power, and Area), design risk reduction and faster time to market.

…

ARM Hard Macros are available in a number of different implementation options with more being added.

Currently the following options are available.

Processor	TSMC 40LP	TSMC 40G	TSMC 28HPM
Cortex-A5 Single-core	X
Cortex-A9 Dual-core		X
Cortex-A15 Quad-core			X

Processor Optimization Pack™ (POP) solutions targeting ARM Cortex™ processors [ARMflix YouTube channel, April 16, 2012]

ARM Artisan Physical IP Delivers Optimized Performance and Energy-Efficiency for ARM® Cortex™-A5, Cortex -A7, Cortex-A9 and Cortex-A15 cores.

ARM Holdings Management Discusses Q2 2012 Results – Earnings Call Transcript [Seeking Alpha, July 25, 2012]

If I look at physical IP, the story here is our physical IP is being used right across the different sectors that ARM’s processors are used in. We’re continuing with the processor optimization package activity. It was a record quarter for POPs. The best quarter we’ve had. So total of over 32 POPs sold now, still about a 50% attach rate with Cortex-A licensees, so that’s good in terms of generating royalty for the future.

[Note that here are only 13 companies shown out of those 32 POP licensees.]

And also good in terms of generating royalty for the future is that this quarter, we had 4 new fabless semiconductor companies adopting ARM physical IP for their 28nm designs and beyond. So that is good for royalty growth going forward.

Note: On the very first “Q2 2012 Highlights” slide one could see the following overall split:

The overall 77% share of processor division comprised of 31% licensing (the lighter blue)and 47% of royalties. So that is a pretty mature part of the business overall, although the Mail GPU part of it is still developing:

Let’s — I should just highlight, we’ve got on the slide, of course, millions now of Mali devices as well, are going into those Cortex-A-based chips. And as far as Mali is concerned, then we are very much on track for the 100 million-plus units that we expect to deliver this year.

as around 180 million Cortex-A units were shipped in the first half alone (see the graph in the next exerpt from the earnings call).

The “Revenue Split Analysis” slide from the Appendix, however, is showing that due to the steadily growing application processor business (simply indicated Processor Division, PD) the share of the Physical IP business (simply indicated Physical IP Division, PIPD) was not growing for the last four years:

With extremely high interest in upcoming technologies of 28nm and beyond more and more Cortex licensees will (should) exploit the POP opportunity. Here is the low-end SoC market leader, MediaTek (Taiwan) example of its upcoming flagship products which should definitely use PoP as well for such a tight delivery schedule (considering the just 10 months availability of Cortex-A7 for licensing, i.e. ~15 months relative to Jan’13 SoC delivery vs. 2-3 years which were required previously):

MediaTek a product roadmap leaked: Quad-core code-named MT6588 [MTK Smartphones Network (MTK手机网), July 27, 2012]
Update: later was renamed and came to market as MediaTek MT6589 quad-core Cortex-A7 SoC with HSPA+ and TD-SCDMA is available for Android smartphones and tablets of Q1 delivery [this same blog, Dec 12, 2012]

From a recently obtained electronic forum information abroad we see that the MT6585 code communicated earlier for the quad-core MediaTek smartphone chipset is wrong. The true model code is MT6588. It is built on the 28nm process in order achieve higher performance level than the dual-core MT6577 technology.

MT6588 has a 4-core CPU [Cortex-A7 (!), see on the second slide below] clocked at 1GHz [1.XGHz rather, see the included slides below, as well the latest rumor about that being 1.7GHz or 1.5GHz], supports dual-channel at maximum 1066Mbps, has an integrated multimode modem for WCDMA [+ it is delivering HSPA+ WCDMA performance (!) vs just HSPA with MT6577/75, see the first slide below] and TD (!), that is it can support both Unicom [latest upgrade to HSPA+ service, see here] and China Mobile 3G network, supports an up to 13 MP camera and 1080P video playback. It finally has a GPU upgrade with SGX544, doubles the resolution to 1280×800 HD level, and has 32KB L1 cache and 1MB L2 secondary cache.

Along the MT6588 there is a 28nm dual-core version, MT6583 on the MediaTek 2012 product roadmap. From the chipset parameters it is evident that MT6583 is a scaled down version of MT6588. It has 2 cores less, the camera support is 8MP, the video decoder is of 720P level, and the resolution is down to 854×480.

It is understood that MT6588 and MT6583 will be in production in the first quarter of 2013, early next year the fastest.

MediaTek to launch quad-core smartphone solutions in 1Q13, says paper [DIGITIMES, Aug 6, 2012]

MediaTek is expected to launch its first quad-core smartphone solution, the MT6588, in the first quarter of 2013, according to a Chinese-language Liberty Times report. The MT6588 features a quad-core 1.5GHz or 1.7GHz Cortex-A7 CPU, supporting WCDMA and TD-SCDMA technologies.

The MT6588, which features a 13-megapixel camera, also supports 1080p video playback and a display resolution of 1280 by 800 pixels. The chip will be built using a 28nm process, the paper said.

Additionally, MediaTek will also roll out a 28nm dual-core solution, the MT6583, during the same quarter. While the dual-core CPU of the MT6853 will also run at 1.5GHz or 1.7GHz, the chip will support a resolution of 854 by 480 pixels targeting a segment different from that of the MT6588, the paper indicated.

Back to: ARM Holdings Management Discusses Q2 2012 Results – Earnings Call Transcript [Seeking Alpha, July 25, 2012]

One thing we are seeing is the value coming through in mobile, generally, the increasing number of smartphones, and within the smartphones themselves, an increasing number of Cortex-A products. And you can see a little histogram halfway down the slide, the top bar there is the ARM11. So ARM11 is still accounting for 40%, roughly, of the apps processors. And the Cortex-A is accounting for, roughly, 60% of the apps processors. But within that Cortex-A, you can see dual-core Cortex-A increasing significantly if you compare the situation with a year ago. And that’s good news from a value point of view for ARM as royalty, because typically these chips are more expensive. So single-core moving to dual-core and quad-core is a good trend for us. And note also, the underlying growth in sheer volume of our apps processors in smartphones. Don’t forget, with all this gloom and doom around, smartphones continues to be an area of significant growth for the business, and we’re looking forward to 30% thereabout growth in smartphones year-on-year so — for the year as a whole.

ARM in MCU and Internet of Things

Growing standardisation around ARM in Microcontrollers
– More than 100 companies have now licensed Cortex-M class processors mainly for microcontrollers, smart sensors and smartcards
– Cortex-M0+ is ARM’s most energy efficient processor for microcontrollers

Collectively, if you look at the line cards from the ARM partners, there are over 1,400 different ARM microcontroller products that you can go out and buy from ARM partners today. And that’s going to be a much bigger number by the time we’re all of that licensing that we’ve been doing gets into Silicon production.

Earlier this year, we launched the Cortex-M0+ product … And again, at the Freescale technology forum, we saw an excellent demonstration of that power efficiency, where they literally had an ARM-powered charger, crank it up with a crank handle, charged a few capacitors up in the range of different microcontrollers and of course, the Cortex-M0+ went on and on and on. So that’s a great product.

As far as the range of opportunities is concerned, it’s huge, and we’re starting to get design ins and as we start to get design ins, so more and more semiconductor companies are jumping onto the ARM-based microcontroller party. And they’re making these decisions in order to position themselves for the Internet of Things way.

Internet of Things brings new opportunities
– Combining radio technology with ARM-based microcontrollers and sensors
– Huge range of applications, billions of opportunities
– New products announced from Freescale, NXP and Toshiba in Q2

In terms of volume shipments, at the moment then we saw another great quarter, where if we look year-on-year on microcontroller shipments up about 20% compared with industry shipments, up about 8%.

Freescale: History & Future of “Internet of Things” – Design West (ESC) 2012 [ARMflix YouTube channel, March 28, 2012]

Jim Trudeau, Solutions Technical Marketing from Freescale on the Cortex-M0+, the Internet of Things and Freescale’s Kinetis L Series

See more: The Internet of Things, the ultimate mashup [Jim Trudeau on Software Meets Silicon blog of Freescale, April 17, 2012], published on ARM blog as “The Internet of Things, a Triad of Partners, and the Singularity of Change”

…

Implementing connectivity is where a company like Motomic Software comes into play. They bring Human Machine Interface (HMI) capability to a new arena. With connectedness comes the need for HMI to get smarter, to display what we really need to know when we need to know it in better ways. Take the lowly thermostat – as simple as its task, a traditional digital thermostat UI is typically confusing to use. A modern, simple UI in a “learning” thermostat can be quite simple. The contrast in complexity is startling as shown in Figure 1.

Figure 1: Contrasting Digital Thermostat UI

…

Motomic Embedded Software Tools for IOT – Design West (ESC) 2012 [ARMflix YouTube channel, March 28, 2012]

Motomic tells us about embedded software tools for applications focusing on Internet of Things, plus a demo of an embedded browser and media grid. http://www.motomicsoftware.com/

See more: A Face for the Internet of Things [Mike Gee, CEO of Motomic Software, Inc. as a guest blogger on Embedded blog of ARM, June 11, 2012 ]

… Motomic has created two browsers. Both browse and render HTML/CSS. Motomic’s µButterfly “microbrowser” runs in as little as ~320 KB Flash and 109 KB RAM. The Butterfly “minibrowser” is based on Qt, it supports features such as TrueType fonts, anti-aliasing and alpha blending. It requires 6+ MB of Flash. The RAM requirement depends on screen size and content requirements, starting around ~1 MB.

Both leverage the very low power requirements and very small footprints of ARM’s Cortex-M0+ and Cortex-M4 microprocessors that are too small to run a web browser such as WebKit, Chrome, Mozilla, etc. These small processors can now accurately render HTML/CSS content previously reserved for higher-end processors.

Qt on Future’s WVGA display [MotomicSoftware YouTube channel, July 9, 2012]

Nokia Qt for Freescale’s MQX real-time operating system on Kinetis K70 @ Future Electronics’ WVGA (800×480) PIM (Passive Intermodulation http://en.wikipedia.org/wiki/Intermodulation#Passive_Intermodulation) displays …. By adding Qt to MQX, you can: develop Qt-based applications for MQX, begin with the latest prebuilt, prevalidated, preintegrated Qt version, ready for your first deployment on one or more hardware platforms—you don’t need to build Qt, add splash screens with the world’s fastest animations, deploy Qt applications to your embedded devices automatically, leverage hardware optimizations and future-proof your hardware platforms. Motomic also lets you add media to MQX, for example advertisements or instruction videos. You can add social networking, games and browser functionality to your applications and products. Motomic helps you distribute your Qt application across networks.

…

Development for the IoT is also being boosted by the Embedded Software Store. Motomic’s browsers and hundreds of other components for developing embedded software are accessible. Pre-built components allow solutions to be assembled more rapidly and with lower project risk. Complex systems can now be built rapidly by adding pre-built components.

Innovative solutions like the Embedded Software Store (source of pre-built components for embedded developers), Motomic’s browsers, and ARM’s range of processors are allowing the creativity of developers to envision and build highly innovative solutions for the Internet of Things.

ARM Embedded Software 2.0 [chipestimate YouTube channel, June 19, 2012]

Will Tu, Director of Business Development at ARM. IP Talks speaker with ChipEstimate.com at DAC 2012 in San Francisco.

See more:
– Advances in technology create new problems for today’s embedded developers [Will Tu on Software Enablement blog of ARM, Oct 12, 2011]
– Solving the Challenge of Software Complexity for Today’s Embedded Developer [Will Tu on Software Enablement blog of ARM, Oct 26, 2011]
– Avnet Electronics Marketing and ARM Launch Embedded Software Store [ARM press release, Oct 26, 2011]

… Users can choose from a broad array of reputable embedded software vendors, including ARM, CMX Systems, Inc., DSP Concepts, Micrium, Motomic, YaSSL, and others. New software vendors are invited to join the initiative on an ongoing basis. The site also offers a quick download delivery system and preview of all license agreements in advance of purchase. Users are encouraged to participate in the Embedded Software Store’s online community to create a strong ecosystem of software support for ARM technology. … The site is fully operational and accessible at www.embeddedsoftwarestore.com …

AvnetEMA and ARM Launch Embedded Software Store [AvnetEMA YouTube channel, Nov 1, 2012]

Kinetis L Series & Energy Efficiency: FTF Keynote Demo [freescale YouTube channel, July 31, 2012]

Freescale Debuts Kinetis L Series, World’s Most Energy-Efficient Microcontrollers [Freescale press release, Jun 19, 2012]

Freescale Semiconductor (NYSE: FSL) is now offering alpha samples of its Kinetis L series, the industry’s first microcontrollers (MCUs) built on the ARM^® Cortex™-M0+ processor. Kinetis L series devices are on display this week at the Freescale Technology Forum (FTF) Americas and were demonstrated during the event’s opening keynote address.

As machine-to-machine communication expands and network connectivity becomes ubiquitous, many of today’s standalone, entry-level applications will require more intelligence and functionality. With the Kinetis L series, Freescale provides the ideal opportunity for users of legacy 8- and 16-bit architectures to migrate to 32-bit platforms and bring additional intelligence to everyday devices without increasing power consumption and cost or sacrificing space. Applications, such as small appliances, gaming accessories, portable medical systems, audio systems, smart meters, lighting and power control, can now leverage 32-bit capabilities and the scalability needed to expand future product lines – all at 8- and 16-bit price and power consumption levels.

The ARM Cortex-M0+ processor consumes approximately one-third of the energy of any 8- or 16-bit processor available today, while delivering between two to 40 times more performance. The Kinetis L series supplements the energy efficiency of the core with the latest in low-power MCU platform design, operating modes and energy-saving peripherals. The result is an MCU that consumes just 50 µA/MHz* in very-low-power run (VLPR) mode and can rapidly wake from a reduced power state, process data and return to sleep, extending application battery life. These advantages are demonstrated in the FTF demo, which compares the energy-efficiency characteristics of the Kinetis L series against solutions from Freescale competitors in a CoreMark benchmark analysis.
*Typical current at 25C, 3V supply, for Very Low Power Run at 4MHz core frequency, 1MHz bus frequency running code from flash with all peripherals off.

…

Features common to the Kinetis L series families include:

• 48 MHz ARM Cortex-M0+ core

• High-speed 12/16-bit analog-to-digital converters

• 12-bit digital-to-analog converters

• High-speed analog comparators

• Low-power touch sensing with wake-up on touch from reduced power states

• Powerful timers for a broad range of applications including motor control

The first three Kinetis L series families:

• Kinetis L0 family – the entry point into the Kinetis L series. Includes eight to 32 KB of flash memory and ultra-small 4mm x 4mm QFN packages. Pin-compatible with the Freescale 8-bit S08P family. Software- and tool-compatible with all other Kinetis L series families.

• Kinetis L1 family – with 32 to 256 KB of flash memory and additional communications and analog peripheral options. Compatible with the Kinetis K10 family.

• Kinetis L2 family – adds USB 2.0 full-speed host/device/OTG. Compatible with the Kinetis K20 family.

The Kinetis L series is pin- and software-compatible with the Kinetis K series (built on the ARM Cortex-M4 processor), providing a migration path to DSP performance and advanced feature integration.

Availability and pricing

Kinetis L series alpha samples are available now, with broad market sample and tool availability planned for Q3. Pricing starts at a suggested resale price of 49 cents (USD) in 10,000-unit quantities. The Freescale Freedom development platform is planned for Q3 availability at a suggested resale price of $12.95 (USD).

For more information about Kinetis L series MCUs, visit www.freescale.com/Kinetis/Lseries.

Kinetis L Series MCUs Built on the ARM Cortex-M0+ Core: What is the Plus For? [freescale YouTube channel, May 4, 2012]

World’s Most Energy-efficient Processor From ARM Targets Low-Cost MCU, Sensor and Control Markets [ARM press release, March 13, 2012]

RM today announced the ARM® Cortex™-M0+ processor, the world’s most energy-efficient microprocessor. The Cortex-M0+ processor has been optimized to deliver ultra low-power, low-cost MCUs for intelligent sensors and smart control systems in a broad range of applications including home appliances, white goods, medical monitoring, metering, lighting and power and motor control devices.

The 32-bit Cortex-M0+ processor, the latest addition to the ARM Cortex processor family, consumes just 9µA/MHz on a low-cost 90nm LP process, around one third of the energy of any 8- or 16-bit processor available today, while delivering significantly higher performance.

…

“The Internet of Things will change the world as we know it, improving energy efficiency, safety, and convenience,” said Tom R. Halfhill, a senior analyst with The Linley Group and senior editor of Microprocessor Report. “Ubiquitous network connectivity is useful for almost everything – from adaptive room lighting and online video gaming to smart sensors and motor control. But it requires extremely low-cost, low-power processors that still can deliver good performance. The ARM Cortex-M0+ processor brings 32-bit horsepower to flyweight chips, and it will be suitable for a broad range of industrial and consumer applications.”

The new processor builds on the successful low-power and silicon-proven Cortex-M0 processor which has been licensed more than 50 times by leading silicon vendors, and has been redesigned from the ground up to add a number of significant new features. These include single-cycle IO to speed access to GPIO and peripherals, improved debug and trace capability and a 2-stage pipeline to reduce the number of cycles per instruction (CPI) and improve Flash accesses, further reducing power consumption.

The Cortex-M0+ processor takes advantage of the same easy-to-use, C friendly programmer’s model, and is binary compatible with existing Cortex-M0 processor tools and RTOS. Along with all Cortex-M series processors it enjoys full support from the ARM Cortex-M ecosystem and software compatibility enables simple migration to the higher-performance Cortex-M3 and Cortex-M4 processors.

Early licensees of the Cortex-M0+ processor include Freescale and NXP Semiconductor. … The Cortex-M0+ processor is ideally suited for implementation with the Artisan® 7-track SC7 Ultra High Density Standard Cell Library and Power Management Kit (PMK) to fully capitalize on the ground-breaking low power features of the processor.

The Cortex-M0+ processor is fully supported from launch by the ARM Keil™ Microcontroller Development Kit, which integrates the ARM compilation tools with the Keil µVision IDE and debugger. Widely acknowledged as the world’s most popular development environment for microcontrollers, MDK together with the ULINK family of debug adapters now supports the new trace features available in the Cortex-M0+ processor. By utilizing these tools, ARM Partners can take advantage of a tightly coupled application development environment to rapidly realize the performance and ultra low-power features of the Cortex-M0+ processor.

The processor is also supported by third-party tool and RTOS vendors including CodeSourcery, Code Red, Express Logic, IAR Systems, Mentor Graphics, Micrium and SEGGER.

Module 1: Kinetis-L Introduction and Overview of Features [AvnetEMA YouTube channel, Aug 3, 2012]

Module 2: Kinetis-L Ultra Low-Power Features [AvnetEMA YouTube channel, Aug 3, 2012]

More information:
– ARM Cortex-M0+: More than a low-power processor [Thomas Ensergueix on Embedded ARM blog, June 19, 2012]: “The Cortex-M0 MCU was quite unique when launched in 2009, offering a subtle mix of low-power, 32-bit performance and optimized code size, all of this packed in a very low gate count processor. … The new implementation of the very same ARMv6-M architecture with a 2-stage pipeline in Cortex-M0+ has given us 9% more performance while reducing the power consumption by around 30%.”
– Introducing the ARM Cortex-M0+ processor: The Ultimate in Low Power [ARM whitepaper by Joseph Liu, May 4, 2012]
– ARM Cortex-M0+ Takes Flight on the Wings of Freescale’s Kinetis L Series [Danny Basler from Freescale as a guest partner blogger on Embedded ARM blog, March 14, 2012]
– FTF 2012 and Everything ARM [Drew Barbier on ARM Embedded blog, Aug 1, 2012]
– The Freedom Board [Erich Styger on Software Meets Silicon blog of Freescale, July 27, 2012]: “… my Freescale Kinetis L series Freedom board arrived. … The board will be available at Element 14/Farnell. It is expected to be publicly available by the end of September 2012, and you can pre-order now. The United States Element 14 site will have the board available for a suggested resale price of $12.95 (USD). In Europe it will be about 10 Euro. …”
– Freescale ARM technology powerhouse in action [The Embedded Beat (all posts) blog of Freescale, June 19, 2012]: “Freescale has become an ARM technology powerhouse, offering the most unique and massively broad portfolio on the market today. It starts with our Kinetis portfolio, and the new Kinetis L series based on the ARM Cortex™-M0+ core, extends to the new Vybrid controller solutions [featuring a unique dual core ARM Cortex-A5 + Cortex-M4 architecture that handles both MCU and MPU tasks on a single chip] that enable rich apps in real time,  and stretches to the ultimate multimedia and display solution – the scalable i.MX 6 series [based on the ARM® Cortex™-A9 architecture].”

Continuing with the ARM Holdings Management Discusses Q2 2012 Results – Earnings Call Transcript [Seeking Alpha, July 25, 2012]

We now have nearly 900 licenses, and so that continues to grow. The pool of licenses that are out there to generate royalties for the future. If I look at just quarter on its own, 23 licenses in total, collection of Cortex-A licenses, including our 12 big.LITTLE licensee. So we’ve now got 12 partners signed up for big.LITTLE. At the other end of this scale, the microcontroller end, I was just talking about the Internet of Things, yes, more licensing of our Cortex-M products.

And our new architecture, the v8 architecture, the 64-bit stuff, we’ve now got 9 v8 licensees, including the latest architecture licensee. And we’ve got this rather, it’s with — rather ill-defined horizontal axis of time going along the slide here. We are at the stage where we’ve done a lot of lead licensing now. We are approaching the first Silicon, the product launch type phase and so the 64-bit program is on track. And the interesting thing about our 64-bit architecture, it is not just about high-end computing and servers, it’s actually people talking about using it and the mobile as well, talking about using it in infrastructure applications, some of the networking applications that I talked about a moment or 2 ago.

ARM in Networking and Servers

• Leading networking companies choosing ARM processor technology
  – Another v8 architecture licensee for intelligent networking applications
  – Freescale announced their first ARM-based chip for infrastructure applications
  – HiSilicon, LSI, TI and Xilinx have already announced ARM-based chips for networking

… these smartphones, computers and everything, they have — they communicate and that communication means that they’re getting data from somewhere or they’re sending data somewhere. They’re sending over some data handling infrastructure. And the explosion in smartphones and more mobile computing and prevalence of the Internet is generating much more data. Some study suggests as much as 20x as much data over the sort of 10-year period from 2010 to 2020. And clearly, if that data is handled with the existing architecture, it’s going to consume 20x as much power, which is not a very sustainable situation. If you look at all the electricity generated in the world, then IT equipment accounts for about 10% of it, and if that is going to increase by a factor of 20, then we’ll going to have to build a lot more power stations. So that isn’t going to happen. People are going to look for more power efficient ways of designing this stuff, and here is the opportunity for ARM in networking. And so you see, as I mentioned a moment ago, a new v8 architecture licensee engaged in ARM in networking.

Freescale, I wasn’t there, Freescale technology forum a few weeks ago. Freescale busy announcing their extensive networking product range, switching to adopt the ARM architecture. We’ve seen similar indications from HiSilicon, LSI, TI, Xilinx and so on. Everybody is realizing that in order to get more power efficient products here, then ARM is a great solution. And it’s the same power efficiency story, which is behind ARM’s activity in servers.

• Servers bringing new opportunities
  – Dell launches ARM-based server with 48 quad-core chips by Marvell
  – Calxeda demonstrated 15x power/performance improvement
  – Canonical announces server grade software for ARM-based chips

ARM Holdings Management Discusses Q2 2012 Results – Earnings Call Transcript, Question-and-Answer Session [Seeking Alpha, July 25, 2012]

Unknown Analyst … you’ve been talking about 64-bits sort of v8 architecture taping out relatively soon. Maybe you could — if you could give us a bit more details on what type of products would come on the market in the next 12 months for these 64-bit, if it’s only servers and other things.

D. Warren A. East

… On the second question, about 64-bits, then as I said in the presentation, it’s being used across a range of different applications, including mobile and computing. Servers is a very visible application area, where as we’ve said before, our penetration in the server market is limited until such time as we deploy 64-bit solutions. And I think it’s well known that one of our early 64-bit architecture licensees is targeting server applications and so probably, you’ll see that Silicon fairly early on. If we move along and move back.

Unknown Analyst I think, Calxeda provided some interesting milestones this quarter in terms of the server progress. I’m just wondering, whether you can talk to how you feel the progress is going there in terms of actual sort of processing. Secondly, I just wondered whether — part of interesting slide just on the multi-core effect in the quarter, I just wondered, whether you have a sense of how much of your units shipped in mobile today is actually on quad-core based devices, versus dual-core, so the impact of quad-core presumably is still to come.

D. Warren A. East

Okay. On Calxeda and the server activity, I really don’t have anything else to say. We’re very pleased with the progress. The data that’s coming out suggests that all the experiments that we did before and all the simulation that we did before is being proven in Silicon. And bear in mind, this first Calxeda Silicon is actually Cortex-A9 based. And so I think I said Cortex-A9 was a core we developed very much with mobile in mind. Calxeda have added System-on-Chip infrastructure to turn into a server chip but it’s still a microprocessor core that was designed for mobile. When you put that server infrastructure around the microprocessor core that’s been a bit more designed with server applications in mind, like for instance, Cortex-A15, or moving onto v8, then you’re going to see even better performance at these levels of power consumption. But we’re very pleased with the data that’s come out so far. We’re also pleased to see other ARM Silicon partners starting to get a bit more public with their activity on the servers. The dual-core, quad-core, I don’t know that I can talk specifically about numbers, but I’ll just point you to shows like Mobile World Congress and CES, where what tends to happen is that you sort of have an announcement about products 1 year, and they turn into reality the next year. And we saw in the 2011 season, a load of dual-core devices being announced and they’ve now sort of materialized into phones. And it was about a year later at these shows that we saw the quad-core products announced and so we’d expect that sort of trajectory to continue. Over and above that, some people have gone a little bit further ahead with the quad-core and they’re using it as a sort of marketing tool and saying that the quad is better than dual. It’s a bit of a marketing thing. And it’s up to us semiconductor partners to see what performance they can actually — for what performance for a given level of power consumption they can actually achieve. We put it up on the slide as multi-core, and put the 2 together, because that’s really how we view it.

Kai Korschelt – Deutsche Bank AG, Research Division
… just on a like-for-like perspective, if you could remind us maybe of the potential royalty premium for a 64-bit versus 32-bit, please?

D. Warren A. East

… On 64-bit premium for — or sort of royalty premium for 64-bit, I mean this is a continuation of the trend we’ve been on for a while, where, basically, if there’s more value in the microprocessor, they royalty comes through with a higher rate. And we’ve talked about Cortex-A being sort of typically in the sort of 1.5% to 2% range, compared with preCortex-A being more in the sort of 1% to 1.5% range. And that trend will continue with our v8 architecture, so it’s going to be at the higher-end of that range.

ARM Holdings Management Discusses Q2 2012 Results – Earnings Call Transcript [Seeking Alpha, July 25, 2012]

64-bit, Physical IP and FinFET

• TSMC and ARM announce collaboration to optimise ARM’s 64-bit processors and Physical IP and TSMC’s FinFET technology
  – Optimization of ARM’s next generation processors and TSMC’s state of the art process technology
  – Companies’ joint work will accelerate the adoption of SoC optimized FinFET technology
  – Allows ARM’s and TSMC’s partners to develop market leading products for high-performance and low-power applications like mobile and enterprise

Now looking ahead to a more leading edge technologies, as I said, we had an announcement earlier this week with TSMC, and this is ARM and the biggest independent semiconductor wafer fab or foundry company in the world getting together to actually continue work that’s been ongoing together for quite a long time, in terms of optimizing their process technology, working with physical IP division to optimize our physical IP on their new FinFET process, and using our new 64-bit processor as a vehicle for that development. So it’s world leading companies getting together to work from transistors right through its microprocessors to enable our joint partners to produce world leading products.

ARM Holdings Management Discusses Q2 2012 Results – Earnings Call Transcript, Question-and-Answer Session [Seeking Alpha, July 25, 2012]

Unknown Analyst

… So on the FinFETs with TSMC, can you give us, maybe a bit more comments about this? How do you think it compares with Intel 3D, or whatever they call it? And how involved your PIPD team is involved trying [ph] to transistors characteristics, absorbs transistors? And also, I think the timing has been brought forward by 1 year, I think. So that’s the first question. …

D. Warren A. East

Dealing with the FinFETs first. A year or so ago, when Intel took technology, we said yes. So this is something which has been around in the semiconductor industry for the last decade or more. It’s one of the ways of making transistors more efficient, but it comes with a load of associated challenges that are actually making this stuff and making them yield and that sort holds back the semiconductor industry from taking that step. Intel took the step and announced that they’ve taken the step. They were the first ones over the gate, announcing that they were doing this. Of course, everybody else has been the same, researching it and playing with it for the best part of the last decade. And TSMC had their plans in place. They just were not choosing to go public on FinFET until they were choosing to go public. And we’ve been working with TSMC on their next-generation processes for some time. We always stood here and done presentations and talked about tape outs on 20nm, the first ARM tape out on 20nm was well over a year ago. We’ve taped out first 40nm designs already with some of these players and its R&D activity. As and when the foundry wants to make some of these things public, then they will, and that’s what TSMC have chosen to do this week. And they chose to, I guess, communicate particularly with their customers who are ARM partners by saying, “Not only are we doing some process development in the back room, but we’re also thinking about how you’re going to take this technology to market, the sort of products you’re going to built with it. You’re probably going to build ARM-based products with it, and so we’ve been working with ARM and ARM’s physical IP division to make sure that their physical IP, their microprocessors and our semiconductor process technology, works well together. And that’s all there is to it.”

…

Janardan Menon – Liberum Capital Limited, Research Division

Two questions. One is on the FinFET agreement with the TSMC, it’s on 64-bit. So I’m just wondering what plans you have on moving the 32-bit, Cortex-A15 kind of products to FinFET? DO you have another agreement with them which we don’t know about and will the timing of the introduction of that be roughly the same as the 64-bit signed? …

D. Warren A. East

Okay. Well, let’s answer the first one. The FinFETs, yes, the announcement is, with our 64-bit processor because just as we want to work with TSMC’s most advanced process technology, they want to work with our most advanced microprocessor, making a 20nm FinFET and later, a 16nm FinFET implementation so that our 32-bit processors will form naturally out of that development activity. We’re optimizing our physical IP to build microprocessors. We just happen to be using our new 64-bit processor as the vehicle for it. The same physical IP will be very easily used to implement our 32-bit processors.

Janardan Menon – Liberum Capital Limited, Research Division

And with your — as part of the timescale of introductions, is that a 2014 introduction or is it ’15?

D. Warren A. East

Well, we have to stick with the announcements for now. And I think as and when TSMC want to make more comments on when these things are available, then they’ll make more comments. As I said, from a development point of view, we’re taping out stuff all the time. …

…

Sumant Wahi – Redburn Partners LLP, Research Division

… The second question has to do with the FinFET again. Am I doing — most of the foundries are sort of offering different known transition and in between, I assume, a FinFET would be, an option in between 20nm and probably 16nm. So my question really was that, would you be licensing FinFET technologies separately as well, or is this an exclusive collaboration with TSMC? And then is there a royalty increase coming from products based on FinFET, PIPD, so to speak? …

D. Warren A. East

Okay. Next question was about FinFET and whether it’s essentially a different physical IP product from ARM. And the answer is, well, it’s a different flavor. We have different flavors of our physical IP for each semiconductor process. And so a low-power version of a given note is a different physical IP bundle than a high-profile version. And the FinFET is another flavor again. So it would be an incremental licensing opportunity. But the fact that our physical IP is used, would generate the royalty opportunity. But it’s not an incremental royalty opportunity. The fact that it’s FinFET, it’s just another flavor. So if we’re going to have a 20nm low-power plainer flavor and the FinFET flavor, and the chips are going to be made out of one process technology, and so the royalty opportunity is the same. …

ARM and TSMC Collaborate to Optimize Next-Generation 64-bit ARM Processors for FinFET Process Technology [ARM press release, July 23, 2012]

TSMC (TWSE: 2330, NYSE: TSM) and ARM today announced a multi-year agreement extending their collaboration beyond 20-nanometer (nm) technology to deliver ARM processors on FinFET transistors, enabling the fabless industry to extend its market leadership in application processors.  The collaboration will optimize the next generation of 64-bit ARM® processors based on the ARMv8 architecture, ARM Artisan® physical intellectual property (IP), and TSMC’s FinFET process technology for use in mobile and enterprise markets that require both high performance and energy efficiency.  

… The ARMv8 architecture extends ARM low-power leadership with a new energy-efficient 64-bit execution state to meet the performance demands of high-end mobile, enterprise and server applications. The 64-bit architecture has been designed specifically to enable energy-efficient implementations. Similarly, the 64-bit memory addressing and high-end performance are necessary to enable enterprise computing and network infrastructure that are fundamental for the mobile and cloud-computing markets. 

TSMC’s FinFET process promises impressive speed and power improvements as well as leakage reduction.  All of these advantages overcome challenges that have become critical barriers to further scaling of advanced SoC technology.  ARM processors and physical IP will be able to leverage these attributes to maintain market leadership, while the companies’ mutual customers can benefit from these improvements for their new, innovative SoC designs. …

ARM and TSMC Sign Long-Term Strategic Agreement [ARM press release, July 20, 2010]

ARM and Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today jointly announced a long-term agreement that provides TSMC with access to a broad range of ARM processors and enables the development of ARM physical IP across TSMC technology nodes. This agreement supports the companies’ mutual customers to achieve optimized Systems-On-Chip (SoC) based on ARM processors and covers a wide range of process nodes extending down to 20nm. …

ARM and TSMC Tape Out First 20nm ARM Cortex-A15 Multicore Processor [ARM press release, Oct 18, 2011]

ARM and TSMC (TWSE: 2330, NYSE: TSM) today announced that they have taped out the first 20nm ARM® Cortex™-A15 MPCore™ processor. The two companies completed the implementation from RTL to tape out in six months using TSMC’s Open Innovation Platform® (OIP) 20nm design ecosystem.

Building on this tape out, ARM will optimize its physical IP technology to specific TSMC 20nm process technologies for Power, Performance and Area (PPA), driving the specification of the Cortex-A15 Processor Optimization Pack (POP). TSMC’s 20nm process provides more than a 2X performance increase over preceding generations.

FINFET: Has its time finally come for a sub – 20nm 3D device? [Jean Luc Pelloie Fellow Director of SOI Technology on the ARM SoC Design blog of ARM, Dec 21, 2011]

… As we move to 20nm and beyond process technology, Fin-FET design may earn its place as the technology path of the future. … Fin-FET or tri-gate may be implemented on either bulk or SOI wafers.  … There is still work to be done, i.e. variability is expected to be different between SOI and bulk versions and needs to be quantified; … However, 3D devices are clearly on the road for sub-20nm nodes…and Fin-FET’s time may finally be here.

Firms Rethink Fabless-Foundry Model [SemiMD (Semiconductor Manufacturing and Design), July 31, 2012]

TSMC, for one, plans to accelerate its finFET efforts. Originally, TSMC planned to introduce finFETs at 14nm by late 2014. Now, the company has no plans to brand its finFETs at 14nm, but rather it will introduce the technology at 16nm. TSMC’s finFET “risk production” is slated for the end of 2013 or early 2014, with production scheduled for the second half of 2015, Chang said.

Taiwan Semiconductor’s CEO Discusses Q2 2012 Results – Earnings Call Transcript [Seeking Alpha, July 19, 2012]

… our 20 nanometer SoC, we believe, is fully competitive with industry leaders, other companies’ 22 nanometer for the served available markets that we serve. For our markets, we believe our 20 SoC is fully competitive with anyone’s 20 nanometer or 22 nanometer offering.

And, one important point to make is that our 20 nanometer has the industry’s leading metal pitch of 64 nanometers. Our leading competitors have 80 nanometer metal pitch. That allows an advantage in the device’s density and die size.

Now, as for the timing, we expect our 20 nanometer technology to be qualified by the end of this year and will be ready to support customers (inaudible) in Q1 of 2013.

Now today, last time I mentioned that we will have a FinFET product after 20 SoC. And today, I’m glad to say that we have been planning the 16 nanometer FinFET. Right after our 20 nanometer (inaudible), which is the 20 SoC, we will offer FinFET at 16 nanometer for significant active power reduction. We expect to achieve speed and density, speed and logic density levels comparable to industry’s leading players 14 nanometer FinFET.

So, we expect our 20 SoC to be competitive with competitors’ 22 nanometer or 20 nanometer products and we expect our 16 nanometer FinFET to be competitive with our competitors’ 14 nanometer FinFET products. You might ask why are we calling it 16. The only reason, in fact, until two days ago, we were undecided on whether to call it 14 or 16 FinFET. Now the only reason we decided to call it 16 FinFET is first, we want to be somewhat modest; second, we are told quite a few major customers ask the 16 FinFET, that designation and we didn’t want to confuse our customers by now switching to 14. But we expect it to be competitive with other people’s 14 nanometer offerings.

Now 16 nanometer FinFET, our 16 nanometer FinFET, is expected to deliver about 25% speed gain given the same standby power over the 20 nanometer SoC. It is expected to give 25% to 30% power reduction at the same speed and the same standby power, and for mobile products, it is expected to give 10% to 20% speed gain at the same total power. As for timing, we expect it to be about one year after 20 SoC namely it should be ready for risk production at the end of 2013 or early 2014, about one year later than the 20 SoC.

[from Q&A session]

… 20-SoC which is 20-nanometer will ramp in 2014. And we believe that the 16 FinFET will ramp in, perhaps the second half of 2015. …

– When sticking with a “David”: CAST Inc.

Decreasing Risk When Selecting Third-Party Semiconductor IP (49th DAC) [castcores YouTube channel, July 17, 2012]

Leapfrogging The Competition Through Smart IP Selection [GSA Intellectual Property blog, March 30, 2012]

Nikos Zervas, VP of Marketing, CAST, Inc.

The adoption of a reliable design reuse methodology, proliferation of high-quality IP products, and shake-out of the most untrustworthy IP vendors creates a situation offering a huge potential advantage to system integrators and product designers looking to jump ahead of their competition.

Instead of choosing the same big-vendor, star IP that most competitors may pick by default, smarter firms will seek out and commit to what might be technically-superior IP products from smaller vendors/partners who will offer both deeper and broader service and support.

A good example is regarding microprocessors and controllers, the heart of most systems and usually the first, most critical system design choice.

Consider a deeply embedded system that needs the power of a 32-bit processor. Much like that saying from the 1980′s that when choosing PCs “nobody gets fired for buying an IBM,” choosing a processor from the leading processor company is probably the easiest, safest choice, and it’s certainly an undeniably fine product with an extremely effective ecosystem. But making this choice might mean missing an opportunity for differentiation in a competitive market where every advantage is required for success.

The IP portal sites list many 32-bit processor core options beyond the leading processor company, with Chip Estimate and Design and Reuse each returning nearly 300 results for such a search. More significantly, I count almost 30 different providers of these products. Certainly some of these vendors offer a product, support, or licensing terms—or perhaps even all three—that could give the smart designer a critical edge.

Six of these stand out as being especially popular based on my recent visits with designers in California and Asia:

• the AndesCore from Andes Technology,
• the BA22 developed by Beyond Semiconductor and available from CAST, Inc. (disclosure: I work for CAST),
• the ColdFire from IPextreme
• the eSi-3250 from EnSilica,
• the LEON3 from Aeroflex Gaisler, and
• the MIPS 4KS and others from MIPS Technologies.

How can you determine if options like these have sufficient benefits to outweigh the risk of not going with the leading processor company? Comparisons can be tricky, but there are a few key points to start with.

The technical suitability and potential advantages of course depend on the detailed needs of your system. A good IP sales team will help you articulate the relevant characteristics of your project and make sure their product will work well before selling it to you.

Quick comparisons of the performance and operating characteristics is made easier through the publication of well accepted power consumption and speed measures, like the CoreMark performance and CSiBC code density standards. Be sure, however, to look deeper to fully understand the specific configuration and technology details behind each vendor’s figures compared to that of your own target system.

Ecosystems for programming and system development aids are a hot processor marketing topic. Be sure that the basics are covered: effective software programming tools such as the GNU tool chain, JTAG debugging, and ports of the RTOS or OS you want to use. A graphical IDE, support from tool vendors like Keil or Lauterbach, and eval/dev board kits are extras that can help further accelerate development.

Licensing terms and actual costs can vary dramatically. For example, some vendors rely on royalty streams for their profits, while others have simpler up-front licensing fees with no royalties. What’s best for you depends on your specific product and market plans.

Finally, credibility of the processor and the vendor are both crucial. For the former, look to successful use by other customers with applications similar to your own. For the latter, look for business longevity and general reputation, backed by your own experiences with the provider’s sales and engineering people. Try to extrapolate from a vendor’s pre-sale support how effective their integration help and other technical support services will be after you purchase from them.

The examples of 32-bit processor alternatives I listed earlier all compare favorably with the leading processor company’s products in these factors; any might be the one to give you the extra technical, timeframe, or cost edge you need to make your product more competitive.

The same is true of most other areas of semiconductor IP. Now that our industry embraces the use of third-party IP, the smartest designers will get a major payback from putting up-front effort into investigating the very best IP for their specific needs, whether that initially seems like the “safe” choice or not.

(Note: all trademarks and registered trademarks mentioned here are the property of their respective owners.)

About Nikos Zervas

Nikos is the VP of Marketing for CAST, Inc. Before joining CAST in 2010, Nikos was a co-founder, chairman, and CEO of video/image SIP vendor Alma Technologies, SA [Pikermi, Greece]. He has been a member of the board for the Hellenic Silicon Industry Association since 2009, and he is a senior member of IEEE. Nikos holds BA and PhD degrees in Electrical and Computer Engineering from the University of Patras, Greece, and has published over forty papers in referenced journals and international conferences.

Additional information:

AndesCore™ from Andes Technology (founded in Taiwan in 2005) with AndeStar™ ISA:

AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to achieve optimal system performance, code density, and power efficiency.

Freescale™ ColdFire Architecture IP