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Majority of Sytem-on-Chip (SoC) products developed in 2011 and 2012, and deployed in market leading smartphone and tablet mobile devices in 2013 have an internal structure similar to this one (which may be considered the most complex SoC of 2013):


That is, a modern SoC is first and foremost designed from a number of commercial IP (Intellectual Property) blocks by a specialist SoC architect with full knowledge of currently available IP blocks as well as the latest expertise of how to put them together in such a way that works. The typical subsystems within a SoC are:
– CPU Subsystem (from ARM, in the above case Cortex-A7 and Cortex-A15 cores with the latest “big-LITTLE architecture”)
– Design-Specific Subsystems: GPU Subsystem for 3D Graphics, DSP (Digital Signal Processor) Subsystem for audiovisual (A/V), Application IP Subsystem, AES (Advanced Encryption Subsystem), 2D Graphics, MPEG, etc.
– Memory Subsystem: …
– the subsystem of High Speed Wired Peripherals: …
– Wireless Subsystem: WiFi, GSM, LTE, LTE Advanced (Mobile Internet)
– Security Subsystem: CryptoFirewall™ (PCF+), RSA-PSS Certified Engine
– the subsystem of I/O Peripherals: …

There are hundreds of IP blocks which are typically coming into these subsystems. The subject of IP blocks themselves you can understand best from The future of the semiconductor IP ecosystem [‘Experiencing the Cloud’, Dec 13, 2012] post of mine. It is only important to note here that the percentage of commercial IP in a SoC has continued to climb, and is usually more than half the chip now. Even more, the use of commercial IP in SoCs can only increase. With each shrink in process node, design teams consolidate what used to be 2 or 3 standalone chips into one chip. This now results in SoCs that have 2 to 3 billion logic gates. In addition to this “chip real estate is cheaper” trend, some companies that solely offered semiconductors are now licensing chip functionality to other SoC makers as design IP.

In the Samsung Exynos 5 Octa die photo below, as an example, you could see how these structural parts look like on the physical SoC (that packaged, which is then put on a circuit board, which comes on its turn into the final device):

Samsung advanced this SoC design even further now, as presented in Samsung Exynos 5 Octa on ARM Mali – Siggraph 2013 [ARMflix YouTube channel, Aug 27, 2013], essentially replacing the GPU Subsystem with a higher performing one in Exynos 5420 (using the Mali GPU IP from ARM) than the one in the Exynos 5410 (using GPU IP from Imagination) introduced for Samsung Galaxy S4 in April, 2013:

Jaeuck Ahn, Marketing Manager, Samsung Electronics, describes the features and benefits of the recently announced Samsung Exynos 5 Octa based on ARM Mali-T628 MP6 GPUs, 4 ARM Cortex-A15 processors and 4 ARM Cortex-A7 processors with ARM big.LITTLE technology. Jaeuck then demos the Exynos 5420 platform versus the Exynos 5 Dual based on the Mali-T604 GPU based Nexus 10 platform showing a 2x improvement in graphics performance.

Such a modern SoC structure is based on the concept of the Network-on-Chip (NoC), where the NoC functionality is implemented (in majority current SoCs) using Interconnect IP products from Arteris. In fact for the SoC enhancements like the above one the NoC functionality is indispensable (although this is not the only benefit of NoC).

Updates 3 years later:

From Low-Power Design Using NoC Technology By Linley Gwennap, May 2015

Network-on-a-chip (NoC) technology is not just for high-performance SoC designs. The size and power of the NoC can scale down to accommodate even very small and low-power processors. Furthermore, the NoC helps automate the chip’s power management. The NoC can also simplify designing a single die that produces multiple end products. This white paper describes how a NoC can achieve these advantages, using TI’s CC26xx microcontroller as a case study. The Linley Group prepared this paper, which Arteris sponsored, but the opinions and analysis are those of the author.

[his conclusion at the very end of the whitepaper:] TI created three different products from the same base design and is able to sell the chip for less than $3. Whether your design targets a list price of $3 or $300, a network-on-a-chip could help achieve your performance and power goals while reducing design time.

From Ncore™ Cache Coherent Interconnect Technology Overview By Craig Forrest and David Kruckemyer on 24 May 2016

Arteris has become the standard for complex and low-power SoCs -- May 2016

Arteris technology is becoming a standard -- May 2016

From Arteris announces 9 new IP licensees in 2015 By Kurt Shuler on February 02, 2016

2015 was an exciting year for Arteris and its semiconductor IP customers. As of December of 2015, there were 101 Arteris-connected SoC designs produced or currently in production, manufactured in a variety of silicon process from 65nm down to to 14nm. Also, 2015 was the first year that Arteris has been designed into in SoCs using 10nm processes.

Arteris delivered two announced new products in 2015: FlexNoC Resilience Package for automotive and industrial applications requiring reliability and safety, and FlexNoC Physical for automated timing closure and physical constraint management at the architectural level. Both new products were licensed by customers and deployed on production SoC projects in 2015. Geographically, the largest design win customer traction came from Asian semiconductor and system houses. In addition, Arteris delivered four new quarterly customer releases for its flagship FlexNoC Interconnect product in 2015.

From Ncore™ Cache Coherent Interconnect Technology Overview By Craig Forrest and David Kruckemyer on 24 May 2016

Arteris interconnect IP now covers coherent and non-coherent use cases -- May 2016

From Arteris Unveils Ncore Cache Coherent Interconnect for Efficient Heterogeneous Multicore SoC Designs By Kurt Shuler, on May 24, 2016

Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced Ncore™ cache coherent interconnect IP version 1.5. Ncore IP is a distributed heterogeneous cache coherent interconnect that allows system architects to efficiently design fully-coherent systems with the advantages of multiple configurable snoop filters and embedded caches, providing greater flexibility than fixed or centralized cache coherency interconnects typically found in today’s SoC designs.

Ncore interconnect IP enhances SoC design configurability by simultaneously enabling different coherent protocol implementations, cache state models and cache organizations. This enables the creation of heterogeneous cache coherent SoCs for fast-moving markets like wireless mobility, HDTV, enterprise storage, automotive advanced driver assistance systems (ADAS), micro-servers and networking.

Version 1.5 of the Ncore interconnect IP enables from one to eight fully coherent agent ports, multiple snoop filters with configurable sizes and agent associativity, and configurable embedded proxy caches (also called “I/O caches”). The architectural limits of Ncore extend far beyond the version 1.5 feature set, allowing a robust roadmap of future Ncore products.

Arteris Ncore IP incorporates configurable proxy caches to increase the performance of non-coherent agents accessing the coherent subsystem, allowing non-cached IP to achieve the benefits of system-wide coherency. Ncore is extremely configurable, enabling designers to select the number of coherent agent and memory interface ports, number and sizes of configurable snoop filters, and number and sizes of embedded proxy caches.

In contrast to fixed or hub-based cache controller implementations, the Ncore interconnect is a distributed solution consisting of replicated units and core components, allowing the interconnect IP to scale to fit a variety of processing requirements. Distributing a hardware architecture in this manner also eases power management, physical implementation and timing closure.

Ncore Benefits

  • Heterogeneous Coherent Agents – Allows simultaneous use of different coherent protocol implementations, cache state models and cache organizations, enabling use of coherent IP from multiple vendors and internal development teams.
  • Distributed Architecture – Eases floor planning and timing closure while enabling the industry’s most flexible clock and power management.
  • Configurable Snoop Filters – Configure the organization, size and association for multiple individual snoop filters based on caching agent characteristics in the system.
  • Proxy Caches – Enable legacy IP to achieve the benefits of system-wide coherency.
  • Scalability – Componentized solution allows efficient scaling to match system requirements.

“We’ve developed Ncore specifically to provide system architects with the increased flexibility and configurability required to efficiently meet application-specific performance goals for the most demanding systems,” said K. Charles Janac, President and CEO of Arteris. “The goal of our Ncore interconnect is to facilitate greater use of cache coherency in the semiconductor industry by enabling accelerators, such as video and imaging processors, to be made coherent with the main central processing units (CPUs).”

See also Arteris Announces Ncore Cache-Coherent Interconnect by Andrei Frumusanu from Anandtech on May 24, 2016

End  of the updates 3 years later

The easiest way to understand the NoC concept is from its first presentation in 2005 (Network on chip eases IP connect [Embedded Systems, March 17, 2005]):


Arteris has developed a complete solution for creating Networks-on-Chip (NoC) which is used to connect and manage the communication between the variety of design elements and intellectual property blocks required in complex system-on-chips. The company’s proprietary IP library uses a packet-based switch fabric in conjunction with its NoC specific design tools to generate unique NoC instances.
Arteris’ proprietary packet-based NoC Transaction and Transport Protocol (NTTP) ensures compatibility with all major on-chip SRAM blocks and socket standards (AMBA AHB, AMBA AXI, OCP 2.0), and also supports key off chip interfaces such as Denali’s Databahn DDR memory controller IP.
The Arteris NoC Solution consists of the Danube Intellectual Property Library that contains a set of configurable building blocks managing all on-chip communications between IP cores in SoC designs, and a suite of design tools for configuring and implementing the IP library as synthesizable RTL.
The Danube IP library is comprised of three types of units: Network Interface Units [NUIs] providing interfaces to the IP cores, Packet Transport Units and physical links building up the switch fabric user-defined topology.
These units can be configured based on the system objectives and topology requirements.

The Arteris NoC solution has beeen widely adopted by SoC vendors since then. Much of the late success of the Chinese SoC design houses could even be attributed to this:

August 13, 2013:
Allwinner Technology Licenses Arteris Interconnect Fabric IP for Tablet and Mobile Device Applications
May 30, 2013:
HiSilicon Using Arteris FlexNoC Interconnect Fabric IP in Multiple Product Lines
May 28, 2013:
RDA Leverages Arteris FlexNoC Interconnect IP for Next Generation SoCs
April 16, 2013:
Rockchip Leverages Arteris FlexNoC Interconnect IP for Next Generation SoCs
February 12, 2013:
Actions Semiconductor Licenses Arteris FlexNoC Interconnect IP for Multimedia Application Processors
July 19, 2012:
Arteris FlexNoC Interconnect IP Licensed by Rockchip for Android™-Based Tablets
February 7, 2012:
Ingenic Licenses Arteris Chip-To-Chip (C2C) IP Solution for Mobile Application Processors
January 10, 2012:
Beijing Nufront Selects Arteris FlexNoC Interconnect IP and C2C for Mobile Phone Systems on Chip (SoC)
November 4, 2011:
Spreadtrum Selects Arteris High-Speed Interchip Communications IP for Mobile Phone Baseband Memory Sharing

As an example of the resulting products here is the range of current Rockchip SoCs and the next generation RK32XX with engineering samples (ES) to come in Q2 2014 (source: Rockchip SoCs Comparison Table, RK32xx Quad Core Cortex A12 Coming Up in 2014 [CNXSoft, July 27, 2013]) as Rockchip was the earliest user of Arteris NoC IP among the Chinese SoC designers currently leading the market there:


Note: Rockchip’s current flagships, the 1.6GHz quad/dual core RK3188/3168 SoCs started sampling in early 2013 and became available in production quantities on June 17, 2013. Rockchip has a strategic partner PiPO (similar to Allwinner’s Onda/Neostra), actually making all products with Rockchip SoCs, also launching first since RK2918 in April 2011. The latest low-end for the current flagship generation is the PiPo Smart-S1 PRO 7.0″ Android 4.2.2 RK3188 Quad-core 1.8GHz Tablet PC with Wi-Fi, 5-Point IPS Capacitive Touch, Auto Screenshot, PIP, Auto Focus (8G) (Black) sold for as low as $110 fm June.

Majority of Leading China Semiconductor Companies Rely on Arteris Network-on-Chip Interconnect IP [Arteris press release, Aug 19, 2013]

Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions, today announced that its interconnect fabric IP has been licensed and deployed in a majority of chips developed by China’s leading semiconductor companies for applications including consumer electronics, smartphones, and tablets. Based on the IHS iSuppli ranking of the top Chinese fabless semiconductor OEMs in terms of revenue, Arteris counts four of the top five OEMs as customers – Spreadtrum Communications, HiSilicon Technologies, RDA Technologies and Allwinner Technology.
According to IHS iSuppli, total Chinese fabless revenue is projected to hit $12.4 billion by 2016, fueled by growth in data processing, wireless communications and consumer electronics. Since 2007, Arteris has focused on the influential China market, offering customers in-country design, development and sales resources. Arteris has enabled its China-based customers – Actions Semiconductor, Allwinner Technology, HiSilicon, Nufront, RDA Microelectronics, and Rockchip Electronics – to improve their design processes and dramatically shorten time-to-market by leveraging FlexNoC interconnect IP. Customers Spreadtrum Communications and Leadcore Technology utilize the company’s C2C chip-to-chip interconnect IP, reducing overall bill-of-materials cost and improving performance.
“We see a very dynamic market in China’s local integrated-circuit (IC) design market, with double digit year-over-year growth projected for 2013,” said Vincent Gu, Principal Analyst, Market Intelligence, with IHS iSuppli. Tools such as Arteris’ network-on-chip interconnect IP fabric enable these design firms to more effectively meet the growing demand for semiconductors in China at a lower cost point.
“Arteris has provided exceptional support to our teams, giving us the confidence to implement the FlexNoC solution in our critical Smartphone SoC platform,” said Li Shiqin, IC Design Manager at Rockchip.
“The Arteris FlexNoC commercial SoC interconnect fabric IP gives us the performance required by our customers,” said Ding Ran, chief technology officer of Allwinner Technology. “We have seen first-hand how the interconnect IP improves process flow and overall system performance.”
“Arteris has achieved significant market share in the China fabless semiconductor market by not only solving our customers’ design challenges, but also by enabling them to quickly adopt best-of-breed technologies and development practices,” said K. Charles Janac, President and CEO of Arteris. “The Arteris interconnect IP fabric technology is one of the most significant SoC cost reduction and productivity innovations of the current decade, based on technology results and market adoption.”
Arteris FlexNoC is the leading interconnect fabric IP chosen because it provides chips design teams with key advantages:
  • Lower chip cost and smaller die area
  • Lower development costs and accelerated time-to-market through shorter design cycles
  • Ability to produce multiple chip versions based on a common SoC platform
  • Greater interconnect speeds resulting in improved performance
  • Reduced power consumption due to advanced clock and power management features, and fewer gates and wires
About Arteris
Arteris, Inc. provides Network-on-Chip interconnect IP and tools to accelerate System-on-Chip semiconductor (SoC) assembly for a wide range of applications. Results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster development of ICs, SoCs and FPGAs.
Founded by networking experts and offering the first commercially available Network-on-Chip IP products, Arteris operates globally with headquarters in Sunnyvale, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm Incorporated, Synopsys, TVM Capital, and Ventech. More information can be found at www.arteris.com.
Arteris, FlexNoC and the Arteris logo are trademarks of Arteris. All other product or service names are the property of their respective owners.

The Chinese were actually starting to use the NoC technology in their SoCs just in time:


Certainly the big name SoC design houses were starting that even earlier:

November 2, 2010:
Arteris Interconnect IP Solution Selected by Samsung for Mobile SoC Deployment
Samsung uses Arteris FlexNoC network-on-chip interconnect technology in its mobile phone applications processors and modems. It also uses Arteris C2C chip-to-chip interconenct IP to easily connect them and allow them to share a single LPDDR DRAM, shortening development cycles and reducing IP compatibility risks.
December 7, 2009:
Arteris raises $9.7M as Qualcomm and ARM join existing investors behind Network-on-Chip (NoC) pioneer
Arteris FlexNoC network-on-chip interconnect fabric IP is Qualcomm’s corporate-standard on-chip interconnect IP for use in mobile and wireless SoC products.
August 8, 2010:
Arteris Network-On-Chip (NoC) selected by Texas Instruments to provide SoC interconnect
Texas Instruments uses Arteris network-on-chip interconnect technology in its OMAP 4 platform of mobile wireless applications processor products.

The now classic SoC from Texas Intruments was first to use the Arteris NoC technology in a complex SoC:

OMAP44x applications processors for breakthrough performance [texasinstruments YouTube channel, Aug 16, 2011]

More information: OMAP™ 4 Processors [TI product page, updates as of Dec 14, 2012]


Arteris customers and Markets:

Mobile Phones and Wireless:
Texas Instruments, Samsung
Video and Imaging:
LG, Texas Instruments, Pixelworks, NTT Electronics, Mobileye, Nethra
Cavium Networks
Custom ASIC Services:
Consumer Electronics:
Altera, Toshiba, Qualcomm, Samsung, LG, Texas Instruments, Pixelworks, MegaChips

Arteris FlexNoC Network-on-Chip Technology Designed into Majority of Mobile SoCs [Arteris press release, June 4, 2013]

Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions, today announced that its FlexNoC interconnect fabric IP was used in a majority of chips developed in 2011 and 2012, and deployed in market leading smartphone and tablet mobile devices in 2013. Smart phones rely on high-performance application processors and LTE baseband modems designed on aggressive schedules, with challenging cost targets, high levels of complexity and leading edge performance. The Arteris FlexNoC interconnect IP solution has been used in such designs since 2007 by market leaders including Qualcomm, Texas Instruments, HiSilicon and other vendors that provide leading SoCs for the highest volume and fastest growing mobility markets.

After calculating the market share positions of those companies and adding the market share from other Arteris mobility customers, Arteris has determined that its FlexNoC interconnect IP solution is in more than 60 percent of application processors and LTE modems by number of SoC projects.
“The Forward Concepts survey titled “Cellphone & Tablet Core Chip Markets ’13” identifies Qualcomm and Samsung as the dominant players in smartphone and tablet core chip markets segments,” said Will Strauss, president of Forward Concepts. “Companies that establish dominant market share at these customers in their respective IP categories will not only see design wins but increasing SoC volume growth. Arteris is staking its claim as one of the companies helping leaders to improve upon their success in bringing market dominating application processors and LTE modems into popular systems and devices.”
Arteris has achieved over 60% project market share in mobility SoC projects by working with market leaders, over the last 3-5 years, to improve their ability to deliver more SoCs with improved technology performance and better gross margins. We are happy to report that the shift to network on chip interconnect IP tool kits for system-on-chip innovation continues to gain momentum,” said K. Charles Janac, President and CEO of Arteris. “The Arteris FlexNoC Network on Chip interconnect IP technology is one of the most significant SoC productivity innovations of the current decade based on technology results and market adoption.”
Arteris FlexNoC is the leading interconnect fabric IP chosen because it provides chips design teams with key advantages:
  • Accelerated time-to-market through shorter design cycles
  • Ability to produce multiple chip versions based on a common SoC platform
  • Greater interconnect speeds resulting in improved performance
  • Reduced die size and cost of chips
  • Reduced power consumption due to advanced clock and power management features, and fewer gates and wires

More understanding comes from Addressing the #1 SoC development challenge with network on chip interconnect technology [designreuse YouTube channel, published June 20, 2012; recorded May 31, 2012 on DAC 2012]

Kurt Shuler is the VP of marketing at Arteris. He has held senior roles at Intel, Texas Instruments, ARC International and two startups, Virtio and Tenison. Before working in high technology, Kurt flew as an air commando in the U.S. Air Force Special Operations Forces. Kurt earned a B.S. in Aeronautical Engineering from the U.S. Air Force Academy and an MBA from the MIT Sloan School of Management.

Network-on-Chip is the backbone of Application Processor and LTE Modem [by Eric Esteve from IPNEST on SemiWiki, May 23, 2013]

I have mentioned NoC adoption explosion during the last two years, illustrated by the huge revenue growth of Arteris. This trend is now confirmed in the fastest moving segments, the Application Processors (AP) and LTE Modem for mobile applications. In fact, Arteris FlexNoC has been integrated in the majority of AP and LTE Modem chips being shipped in 2012 and shipping in 2013. What is the common and key feature for these chips?


Each of these is shipping by dozen of millions, all of them are extremely complex, counting 100 IP or more, and the Time To Market (TTM) is dramatically important: if a chip maker miss the release to production by only one months, several dozen if not hundred $ millions of chip sales just vanishes… and will never be catch-up, because OEM integrating these IC like Apple, Samsung or HTC have to release a new product generation almost every 6 months. If you take a look at the business won by Arteris since 2008, you will name most of the major semiconductor companies (even if you are not supposed to know the name of “Unannounced Customer”, just think about “Major”…).


If you come back to one of my very first post about Network on Chip, you remember that one of the most important NoC advantage is to avoid routing congestion on large SoC, thus accelerating TTM as the back-end cycles (Place and Route/post routing simulation/modification) are extremely time consuming. But we know that for IC like AP and LTE Modem, the key sales message will be about Performance, measured in term of main CPU Frequency, and Low Power, as these will be the most visible feature for the end user: can I use my smartphone right after opening it? Do I need to plug it every two hours or could I use it for days before charging? Arteris’ FlexNoC is also addressing these two very important requirements that every chip maker has… or that the company should have, in order to be successful!



  • FlexNoC™ -For high performance SoCs (Wiki)
  • FlexWay™ – For smaller SoCs (Wiki)
  • C2C™ Chip to Chip Link™ – For connecting multiple chips and dies (Wiki)

It’s very interesting to see that the very fast growing chip makers or ASIC companies are also adopting the NoC, and the reasons why they adopt Arteris’ FlexNoC: high frequency, low gate count, lower power, higher flexibility or Quality of Service (QoS) are the most frequently mentioned advantages.

Fuzhou Rockchip Electronics Co. Ltd.
“Arteris FlexNoC interconnect IP enables us to exceed our design frequency and power requirements while giving us more flexibility than possible using older interconnect technologies, like buses and crossbars,” said Li Shiqin, IC Design Manager at Rockchip.

MegaChips Corporation
“From our experience with Arteris’ NoC technology over the years, we knew that Arteris FlexNoC IP was the fastest interconnect fabric for SoCs with multiple initiator and target IP blocks. However, we were surprised that FlexNoC could continue to run at fast design frequencies with a significantly lower gate count and less power consumption than alternative bus fabrics,” said Gen Sasaki, General Manager of Division No.2, MegaChips Corporation.

Open-Silicon, Inc.
“Arteris’ network-on-chip interconnect IP made timing closure much easier and allowed us to implement the QoS management required for the design’s high-performance I/O and sophisticated hardware acceleration engines. In addition, we were able to close timing in a fraction of the schedule needed previously for designs using older crossbar-based architectures,” said Colin Baldwin, senior director of marketing, Open-Silicon

[The not readable logo is: image_thumb[31] i.e. Ingenic Semiconductor Co., Ltd.]

When you see such a customer list, you understand why the company is claiming that FlexNoC is integrated into about 60% of the Application Processor and LTE Modem IC. When you know the associated shipments in smartphones and media tablet applications, you can guess that Arteris royalty revenues will sky rocket in 2013 and after!

To learn a lot more about NoC and Arteris products, just go here.

Related Pages:

NoC Interconnect Technology Becoming Mainstream [by Kurt Shuler on Arteris Connected Blog, Aug 31, 2011]

Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip (SoC) market over the last couple of years.

As reported by EE Times, Gartner’s latest “Hype Cycle for Semiconductors” shows Network on Chip technology climbing the “slope of enlightenment” after its sojourn in the “trough of disillusionment.” As SoCs have become more complicated, SoC makers like Texas Instruments, Toshiba and LG have chosen to use NoC technology to proactively address wire routing congestion issues, timing closure failures and the need to easily create derivative SoCs based on a single SoC.


Gartner Hype Cycle graphic source: Gartner Group and EE Times

“Network on Chip”: Words mean something.

As with many new technologies, an early impediment to adoption was semantic: What is a “network on chip?”

It seems obvious today that a network on chip interconnect digitally packetizes information, allowing it to travel over paths of varying bit widths. If done intelligently, the NoC technology will be based on small elements that are physically distributed throughout an SoC floor plan. This is in contrast to traditional crossbars and switches, which are monolithic IP blocks that are hard to fit in the white space between IP blocks without causing routing congestion and timing closure problems.

A few years ago, confusion reigned in academia and commercial marketing about the definition of a NoC, with some defining it down to include any type of interconnect technology: Hierarchal busses, smart switches, crossbars, etc.

But a strict definition requiring data packetization and serialization won out. Today you’ll find marketers trying to wiggle out of that old semantic trap by putting the adjective before the noun, using “on-chip network” to describe any type of interconnect.

Technically correct. But using this logic, two tin cans and a string are a “communications network.”

Commercialization leads to mainstream technology

Besides resolving confusion around naming, what is the key factor that helps make a technology mature enough to be considered mainstream?


By commercialization, I mean that painful process where a technology is used by a lead customer, refined, then used by a larger set of customers and polished some more. This cycle continues until the technology is robust enough and complete enough to meet the needs of a large percentage of an emerging addressable market.

Geoffrey Moore’s “Crossing the Chasm” is a great book that describes the sequential steps a new technology must go through before it becomes mainstream, as well as the need for a market infrastructure to develop to support it.


Technology adoption life cycle graphic source: Geoffrey Moore, “Crossing the Chasm”

This cycle, called the technology adoption life cycle, holds true for any new technology, whether we are talking about the wheel (which also required roads, carts and draft animals to achieve huge productivity gains), canned food or the fax machine.

Network on chip technology also went through this technology adoption lifecycle, with early “innovators” demanding a new interconnect technology to address their then-bleeding edge needs. An example is Texas Instruments’ OMAP team, which needed a more scalable interconnect for their OMAP mobile application processors as each grew in complexity. TI is an innovator for having started using NoC technology nearly 5 years ago.

In the following years, “early adopters” started using NoC technology, providing more feedback that helped shape it into a complete solution for SoC interconnects of any size or complexity. This made the NoC technology “safe” for the more conservative “early majority” companies to adopt.

The future of NoC technology for SoCs

What does the future of network on chip technology look like?

Adoption of NoC interconnects by SoC makers is expected to increase quickly during the next couple of years.

Current users of NoC technology chose this solution because they were already experiencing SoC routing congestion, timing convergence and derivative creation problems and they needed a practical solution. More SoC makers will have these problems in the next two years as the most advanced mainstream semiconductor manufacturing processes shrink below 40 nm, allowing SoC designers to put even more functionality (and IP blocks) on a single SoC.

Adding more IP blocks causes routing and timing issues to increase at a non-linear rate, causing excruciating pain to back-end engineers and delays in chip schedules. The only way to address the problems caused by adding more IP blocks is to use an interconnect technology that is scalable, packetized, low power, and high performance while providing end-to-end quality of service and accommodating any type of transaction protocol. These requirements can only be met by commercial network on chip interconnect IP.

How to solve the “Too Much Semiconductor IP” problem? More IP! [by Kurt Shuler on Arteris Connected Blog, June 19, 2013]

When discussing system-on-chip (SoC) design with my semiconductor design and software development peers, the conversation eventually gets around to the problem of, “There’s just too much IP!” The feelings I hear border on exasperation at the problem of integrating IP on today’s large SoCs. Engineers who were once paid to write lines of Verilog or C code from scratch are now spending much of their time tying together commercial hardware IP and the associated software. Their jobs have changed, and they’ve had to acquire new skills and new tools to be successful.


Samsung Exynos5 Octa die photo – Arteris FlexNOC

Stepping back for a second, one could assume that all the semiconductor industry consolidation has resulted in fewer commercial IP choices (See “The Semiconductor Industry Needs an IP Switzerland”, http://info.arteris.com/blog/bid/96393/The-Semiconductor-Industry-Needs-an-IP-Switzerland). And that would be wrong. Even though there are fewer small companies offering design IP, the percentage of commercial IP in a SoC has continued to climb, and is usually more than half the chip (depending on how you measure it: logic gates, monetary value, etc.).

The use of commercial IP in SoCs can only increase. With each shrink in process node, design teams consolidate what used to be 2 or 3 standalone chips into one chip. This now results in SoCs that have 2 to 3 billion gates. In addition to this “chip real estate is cheaper” trend, some companies that solely offered semiconductors are now licensing chip functionality to other SoC makers as design IP.

Given that the use of commercial design IP will continue to grow, the problem becomes how to integrate it. Part of the problem can be addressed with the help of existing means such as increased automation, standardized IP information schema (like IP-XACT), and greater use of system-level modeling. All these means are discussed in the article, “Integration Demands Automation” by Ann Steffora Mutschler (http://chipdesignmag.com/sld/blog/2013/01/31/integration-demands-automation/).

However, the most important means to address the problem of integrating hundreds of IP blocks is to smartly use another IP: The interconnect fabric.

The interconnect fabric is the one IP that touches every subsystem and every functional block on a chip. When the design team configures the various IP blocks on a chip and ties them into the interconnect, this information (configuration options, transaction protocols, memory locations, etc.) can be stored by the interconnect IP and associated tools and used to automate the creation of system models, verification environments and even software drivers. In effect, the interconnect fabric acts as the “golden model” that describes the assembly parameters of the SoC.

Therefore, the way to solve the “more IP” problem is to carefully select what is the most important IP with regards to SoC assembly, modeling and verification: The interconnect fabric.

System-Level Design Arteris CTO interview: Faster IP Integration [System-Level Design, April 25, 2013]

By Ed Sperling
System-Level Design sat down with Laurent Moll, chief technology officer at Arteris, to talk about interoperability, complexity and integration issues. What follows are excerpts of that conversation.

SLD: What’s the big challenge with IP?
Moll: Interoperability is always a concern. Because of ARM’s dominance, a lot of people are moving to AMBA protocols, whether that’s APB or AXI. The bigger companies typically have something they’ve developed internally, or an existing protocol they’re using. They tend to still have a sizeable legacy piece. They will move away from that eventually, but it will take time. Anytime the entire environment is built around that, it takes a while. The only other thing we have involving interoperability are port interfaces for memory controllers. There’s a lot of baggage around there.

SLD: But there also are lots of little processors on an SoC, too. What impact does that have?
Moll: There are lots of things happening in a modern SoC. In mobile SoCs, there are subsystems for cameras, video and a lot of hardware acceleration. They started from the main CPUs from ARM and it trickled down to the subsystems, and that’s taking over a lot of the SoC. From a verification perspective and an assembly perspective, people don’t want to deal with too many things. So if one of them is dominant, you might as well use it as often as possible.

SLD: Where does the network on chip technology fit in?
Moll: It’s everywhere. We like the fact that people are standardizing, because if IP comes in with a standard protocol like AMBA it means we can connect to it more easily. What happened before was people were essentially growing chips rather than assembling them. It meant that the interfaces to all the IP blocks were custom. It was hard scale beyond a certain point.

SLD: So what you’re starting to see are the first signs of a maturation of the commercial IP business?
Moll: That’s correct. A lot of companies have moved to a model where, instead of having one flat organization, it’s more of a silo-type of organization where you have a lot of people building subsystems and a separate group assembling them. This whole process, as we see it, is the maturing of the industry. It’s possible to assemble a chip. It’s not easy, but it is the fastest and most efficient way.

SLD: Does that make it easier to choose one IP block versus another?
Moll: Absolutely. People can try different things. They can swap them in and out very easily. And we’re also starting to see virtual prototypes where the software vendors are building hardware that will never actually tape out. But they can test their software and how it works with different pieces from different vendors. This is the first time we’re seeing platform assembly bubbling up the food chain to people building software or systems. If you’re Microsoft, for example, for Windows 8 you can build a virtual platform with a NoC and test out how it operates on an ARM processor or a GPU. This platform will never exist in reality, but it can run tests, it can run software stacks and you can shop it around to vendors. It is part of the maturation.

SLD: If you’re comparing one piece of IP to another, what is it like today versus five years ago?
Moll: Five years ago, a lot of IP was internal rather than commercially available. Interoperability was a problem. You had this thing that you grew internally that didn’t connect to anything very easily. Then you had this other IP with a standard interface and you couldn’t connect them. People still build internal IP, but they build them in a way that they can be connected easily. Even now nothing connects seamlessly. AMBA helps because it’s a standard, but it’s more of a catalog of things you could do with the interface. So there is still a lot of tweaking. You can connect them in a basic fashion. But if you really want take advantage of all of this IP, there are still some nuts to turn and things that are necessary to make them work together really well.

SLD: Is the goal lower NRE [Non-recurring engineering] or time-to-market improvements with the same NRE?
Moll: For the consumer markets, time to market is everything. And it’s time to market not just for the first chip and making sure it works, but also for the 10 derivatives they’re going to make. In the past, it was like a butcher shop. You had to cut things up carefully and make sure it all still worked. Our largest customers can just crank out derivatives where most of the work is on the back end. The interconnect is in place, and they just take one thing off and replace it, re-do all the performance regression and they’re done. NRE is less important for them, because when you’re doing large volumes that doesn’t show up. Missing one day on the market does.

SLD: That’s time to market in a small slice of a market, too, right?
Moll: Absolutely, and this is why platforms are so important. Making very big chips work well is still a difficult process. You still have to worry about performance, use cases, power, security, and all these types of things. So it takes awhile to get a big platform together. But once you have one that works, you can create derivatives, shrink it, and customize it for all these niches very quickly. That’s where the time to market comes into play.

SLD: There has been a lot of talk about platforms over the years, but they’ve been slow to catch on. What’s changed?
Moll: With the most complex chips, people are moving to platforms. There is so much NRE invested into one thing that you want to be able to get your return. There is a lot of verification and checking the back end to make sure it works. You want to make sure this one thing works really well, and then you use it for two years or three years. You get quite a bit of use out of it. So it’s true that platforms aren’t universal yet, but we do see them with companies that need to build one really complex thing. They invest in a platform so they don’t have to invest a lot of money and time in derivatives.

SLD: We’re starting to see the rise of subsystems, which are a step in that direction.
Moll: Subsystems have been around for quite some time. The subsystem is, in many ways, a political entity in many companies. It’s a silo issue. So the guys in imaging are all the guys who know imaging. The guys in 3D are all the guys who know 3D. They tend to have their own requirements. If they need a microcontroller, they go around the company looking to see if there’s a microcontroller. Or do they contract with ARM for an M0. That has existed for a while. What’s newer is that the interface to that subsystem is becoming standard, and the components inside the subsystem are becoming standard. For the interconnect, we’re finding that companies are using our technology between the subsystems as well as inside the subsystems. When you assemble things that are built to work together, the probability is higher that they will work.

SLD: IP has always been a black box, and subsystems increasingly are collections of IP. What does that do for connectivity?
Moll: It depends on the subsystem, which can look completely different. For a security subsystem, where you have CPU, an SRAM and a bunch of devices, this is like a small system, so it’s better to have transparency. When you get into QoS and security, at the top level it’s easier to understand if it’s not a black box. Otherwise you may have to spend time looking at an interface and trying to understand what that interface does. We see that in the subsystems where the interconnect is used for what look like small systems. For a CPU, there are a bunch of things that hang together in a very specialized way. They don’t look like subsystems. They’re just a big block and there’s an interface to them.

SLD: If you’re creating an SoC with a NoC, where are you seeing issues in connecting everything up?
Moll: In the past five years there is a new job description called SoC architect. Before that there was just a chip architect. So for this new job, you have a bunch of IPs. You know what’s inside some of them and some of them you don’t, and your job is to put them together in such a way that works. The reason why this job exists is that the whole thing flattened it way too complicated, just as people 20 years ago realized that flattening the whole netlist to make a chip isn’t going to work as well. At the architectural level, the problems are transversal, such as power, performance, security and debug infrastructure. Something like a standard interconnect helps you solve a number of those issues. Then you just have to verify that it does what you want. The other thing involves all the stuff at the back end, which is also an assembly process. You also have subsystems, which may look different from the others. Some have hard macros, others don’t. There’s a whole top-level assembly process of all your clock-domain crossings, power domains, DFT. The assembly issue is making these cross-functional topics work together. That’s where you spend a lot of time, and then verifying everything.

SLD: The new wrinkle in this is software, which can interact at many different levels. Does the network now have to account for the software?
Moll: When you’re building your own RTL, it means it won’t be ready for software until late in the process. If you’re assembling parts, you can start assembling the chip early. You either have functional or RTL models, and you can create a virtual platform way before tapeout. We see a lot of people doing that. The advantage for the NoC is that you have RTL right away. It may not be the final RTL, but functionally for the software guys it’s good enough.



  1. […] pillanat van, mivel a Nyugat most már SoC (System-on-a-Chip), azaz rendszerchip szinten is kénytelen elismerni a kínaiak verhetetlenségét (azaz vége az […]

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