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TSMC’s 16nm FinFET process to be further optimised with Imagination’s PowerVR Series6 GPUs and Cadence design infrastructure

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OR After CPU level optimisation With 28nm non-exclusive in 2013 TSMC tested first tape-out of an ARM Cortex™-A57 processor on 16nm FinFET process technology [‘Experiencing the Cloud’ April 3, 2013] the world #1 foundry decided to further optimise its crucial 16nm FinFET process with the most demanding from implementation point of view PowerVR Series6 GPUs for graphics and compute applications

Update: TSMC 16nm FinFET to enter mass production within one year after 20nm ramp-up, says Chang [DIGITIMES, April 18, 2013]

TSMC’s 16nm FinFET process will enter mass production in less than one year after ramping up production of 20nm chips, company chairman and CEO Morris Chang said at an investors meeting today (April 18).

Chang indicated that TSMC already moved its 20nm process to risk production in the first quarter of 2013. As for 16nm FinFET, the node will be ready for risk production by the year-end, Chang said.

While stepping up efforts to bring newer nodes online, TSMC has revised upward its 2013 capex to US$9.5-10 billion. The foundry previously set capex for the year at US$9 billion.
In addition, Chang reiterated his previous remark that production of TSMC’s 28nm wafers and revenues generated from the process in 2013 will triple those of 2012. The node technology will continue to play the major driver of TSMC’s revenue growth in 2013, said Chang, adding that the foundry’s share of the 28nm foundry market will remain high this year.

The essence:

… As part of this new phase of their relationship, Imagination will work closely with TSMC to develop highly optimised reference design flows and silicon implementations using Imagination’s industry-leading PowerVR Series6 GPUs combined with TSMC’s advanced process technologies, including 16-nanometer (nm) FinFET process technology.
Imagination and TSMC R&D teams will also work together to create fully characterised reference system designs, utilizing high bandwidth memory standards and TSMC’s 3D IC technology capability to demonstrate new levels of system performance and capabilities while retaining all the essential characteristics of power, silicon area and small package footprint demanded by high volume mobile SoCs. …

… “Just as memory drove silicon processes in the ‘80s and ‘90s, and CPUs drove processes further in the late ‘90s and ‘00s, high performance mobile GPUs for graphics and compute applications are one of the major drivers for our most advanced process technologies,” says Dr. Cliff Hou, TSMC Vice President, R&D. “We’re pleased to be working with Imagination, an established leader in mobile and embedded GPU IP, to understand how best to use PowerVR GPUs to work with us to optimize future generations of our most advanced process technologies, and advanced system design techniques.” …

This close cooperation will significantly help TSMC to reach mass production at 16nm node in H2 2014 at the latest, as shown by the advanced technology ramp-up information at TSMC given below:

Back in November it was reported that TSMC 16nm FinFET rollout to come earlier than expected, says Digitimes Research analyst [Nov 8, 2012]:

Taiwan Semiconductor Manufacturing Company (TSMC) is expected to ramp up 20nm production ahead of schedule, and also put its 16nm FinFET process into production far earlier than expected, according to Digitimes Research analyst Nobunaga Chai.
Chai indicated that information revealed by TSMC at its most-recent investors meeting clearly shows that the foundry has made significant progress in the development of advanced process technology, especially its first FinFET process that will be at 16nm. TSMC’s 16nm FinFET process should be able to enter mass production in less than one year after ramping up production of 20nm chips, Chai predicts.
Speculation has been circulating that TSMC’s 20nm process will help the foundry attract its first orders for application chips from Apple. Chai said that he expects TSMC’s 16nm FinFET process to play an important role in Apple’s “breakthrough” product. TSMC’s 20nm process is likely to grab orders for Apple’s next processor, which could be merely an upgrade of the existing A6 version.
During a Q&A session at TSMC’s recent investors meeting, company CFO Lora Ho revealed that the foundry’s 20nm process has received around 50 product tape-outs – about one-fifth of TSMC’s previous tape-outs using 28nm process. Ho added that actual production at the newer node will not kick off until 2014.

As for 16nm FinFET, TSMC chairman and CEO Morris Chang disclosed that the company expects to start “risk” production of the process in November 2013, followed by mass production a year later.

and a few days ago came the news that TSMC to install 20nm fab equipment ahead of schedule, says report [DIGITIMES, April 2, 2013]

Taiwan Semiconductor Manufacturing Company (TSMC) plans to begin installing production equipment at its 20nm-capable facilities on April 20, about two months ahead of schedule, according to a Chinese-language Economic Dailys News (EDN) report.
Following the equipment move-in, TSMC is expected to tape out SoC products at 20nm around the end of the second quarter with initial capacity of 5,000 12-inch wafer starts per month, the report cited unnamed fab tool suppliers as indicating. The new technology node is set to enter volume production in the third quarter with monthly capacity reaching more than 10,000 wafer starts, the report said.
TSMC internally set a target of growing its capacity for 20nm products to 30,000-40,000 wafer starts monthly by the end of the first quarter, 2014, the report noted.
TSMC in April 2012 disclosed that its 20nm technology would begin volume production at Phase 6 of its Fab 12 wafer fab (Hsinchu, northern Taiwan) in 2013, and Phase 5 of Fab 14 (Tainan, southern Taiwan) will be the foundry’s second 20nm-capable fab, which is scheduled to enter volume production in early 2014.
TSMC also began construction on Phase 3 of Fab 15 (Taichung, central Taiwan) in September 2011. The module will be TSMC’s second gigafab equipped for 20nm process technology. The foundry has not provided a timeframe to volume produce 20nm products at Phase 3 of Fab 15, but already set the initial capacity at 40,000 wafer starts per month.

The evolution which led to the crucial TSMC-Imagination-Cadence collaboration at the 16nm node was:

TSMC OIP 2012 – David Harold (Director of PR, Imagination Technologies) interview [chipestimate YouTube channel, Oct 26, 2012]

Sean O’Kane, Producer/Host ChipEstimate.TV interviews at TSMC OIP (Open Innovation Platform) 2012 John Blyler, Editor-in-Chief, Chip Design and Embedded Intel magazines David Harold, Director of PR, Imagination Technologies. See Latest Imagination Technologies IP at http://www.chipestimate.com/prime-partner/211/Imagination-Technologies-IP-Catalog

Implementing and Optimising Graphics IP in SoCs [Imagination Technologies presentation at TSMC OIP 2012, Oct 16, 2012] by Steven Riddle

Abstract

As major IP blocks such as GPUs increasingly dominate the area, power and performance of next generation SoCs, traditional “Soft IP” fully synthesisable, process-neutral solutions need to be re-evaluated to maintain the optimum balance between maximum portability and maximum performance. In this paper, we will discuss the techniques being used by Imagination and its partners to address some of the highest performance corners of this envelope, and how the characteristics of the latest processes such as 28HPM and beyond are being taken increasingly into account when designing future Soft IP high performance solutions.

Imagination highlights how GPUs are driving silicon performance and SoC innovation [press release, Oct 16, 2012]

Imagination’s engineers to present paper on GPU Optimisation Techniques at TSMC’s Open Innovation Platform Forum
San Jose: Imagination Technologies, a leading multimedia and communications technologies company, observes that the growth in performance of mobile GPUs, such as its PowerVR IP cores, is driving future generations of silicon process and packaging technologies, as well as SoC (system on chip) processing performance across a growing range of markets.
The GPU’s ability to deliver unprecedented processing horsepower (measured in GFLOPS) whilst also delivering amazing graphics performance per mm2 and per mW, means that GPU capabilities are becoming the dominant force driving heterogeneous processing performance in everything from mobile phones through to TVs, in-car information and entertainment, games consoles and even cloud computing.
Recognising this trend, Imagination is further developing its roadmaps, architectures and support to ensure its partners can select IP solutions optimized for the latest silicon process and SIP (System in Package) technologies, enabling them to realise the full potential of what GPUs can deliver in SoCs, both for graphics and compute capabilities.
To help its partners, Imagination is already working with leading silicon foundries to implement high performance mobile GPU-based systems delivering unheard-of levels of memory bandwidth, using the latest PowerVR Series6 GPUs combined with wide I/O memory and advanced 3DIC assembly and process technologies. Imagination is also working with foundries and EDA vendors to ensure that licensees of all of Imagination’s IP (intellectual property) cores can benefit from well-defined tool flows and optimized libraries to achieve the most aggressive speed, area and power consumption targets.
Reflecting closer ties to key foundries, Imaginations’ engineers will be speaking at the TSMC Open Innovation Platform Forum 2012 in San Jose, CA, on ‘Implementing and Optimising Graphics IP in SoCs’. Imagination will also be demonstrating its latest PowerVR GPU and VPU (video processor) as well as Ensigma RPU (radio processor) and Meta CPU IP technologies at the event (booth 201).

Says Tony King-Smith, VP marketing, Imagination: “Just as memory drove silicon processes in the ‘80s and ‘90s, and CPUs drove these in the late ‘90s and ‘00s, mobile GPUs are now becoming the most demanding on-chip function driving tomorrow’s advanced SoCs and silicon processes. We see our strengthening relationships with leading foundries, EDA vendors and library providers, as well as strategic activities with industry standards bodies such as HSA Foundation and Khronos Group, as key to ensuring we continue to drive and deliver the leading edge capabilities our customers have come to expect from us.”

More information:
Imagination Technologies will boost mobile graphics performance through customization [VentureBeat, Oct 15, 2012]

… Imagination usually gives a “synthesizable core,” or a ready-to-go finished design, to its chip licensee partners. The partners take that core and incorporate it in their chips and take it to a foundry partner, which makes the chip. The change now will be that Imagination will optimize its cores for a particular foundry’s factory, such as a 28-nanometer manufacturing line at TSMC, so that the resulting chip will be faster and use less power.

“We’re doing this because our customers are asking for it,” said Tony King-Smith (pictured), vice president of marketing at London-based Imagination Technologies, at a press briefing in San Jose, Calif. “They say they want a chip tuned to a particular foundry.”
King-Smith said the result would be faster and lower power chips, but he couldn’t quantify how much. …

Imagination tools graphics cores for 28 nm [EETimes, Oct 15, 2012]

Imagination is working with EDA tool and library developers as well as foundries to help optimize the physical layout of its GPUs. However, the company currently has no plans to sell hardened macros.
New capabilities will span a broad range of chip design areas including standard cell libraries, voltage scaling in process nodes and clock-tree optimization, Tony King-Smith, vice president of marketing at Imagination, said here the day before the opening of the TSMC event. “People are asking us to do more process tuning,” said King-Smith. “We will not deviate from our IP being fully synthesizable, however we will complement it more and more with tuned libraries and tool flows.”
“We are making the design more aware of the process with hints in the design database itselfmost library vendors with an open mind will be talking with us,” King-Smith added.
Hard macros are rarely used because “no one has the same [chip] floor plan, so it’s better to tune up the flows and libraries so people can harden the designs themselves more effectively,” he added.
The extent of improvements in reduced power consumption, area or increased performance will vary greatly among design teams, depending on the time they put into the optimizations, he said, declining to provide any hard figures.
Foundries as well as SoC designers are driving the demand for more optimization, he said.  Most of the effort is now going on at the 28-nm node, but programs have started at 20- and 14/16-nm nodes using FinFETs, he added.
“The foundries are coming to us when characterizing 28- or 20-nm nodes looking  for reference designs for what will push their processes,” said King-Smith. “Historically, it has been memory and processors [in that role but] now GPUs are consuming the most area and power on the chip,” he said.

Imagination Optimizes its IP Capabilities with TSMC on Latest Silicon Process Technologies [press release, June 14, 2012]

Imagination Technologies, a leading multimedia and communications technologies company, announced its collaboration with TSMC to ensure that licensees of all of Imagination’s IP (intellectual property) cores can optimize speed, area and power consumption on TSMC’s most advanced 28nm and below processes.
By bringing together engineers from both companies, this collaboration aims to improve power, performance, and area by co-optimising TSMC process technologies and foundation IPs with Imagination’s most advanced IP cores, including its latest PowerVR GPUs.
Imagination, a member of TSMC’s Soft-IP Alliance program, is making this announcement as part of a closer relationship with TSMC. Imagination intends to validate its IP cores through the TSMC Soft-IP Alliance program.
Imagination’s IP core families in this collaboration include:
  • PowerVR graphics, the de facto standard for mobile, embedded and computing graphics
  • PowerVR video and display, the comprehensive and widely adopted range of multistandard decoder, encoder and enhancement cores for applications from mobile to ultra-HD
  • Ensigma communications, the multi-standard programmable communications and connectivity technology for TV, radio, Wi-Fi and Bluetooth
  • Meta processors, the advanced 32-bit hardware multi-threaded processor architecture that delivers the best in both general purpose and signal processing performance
Imagination is one of the world’s leading semiconductor IP suppliers, with cores which can be synthesised for a broad range of silicon processes. As more customers use Imagination’s IP cores to deliver the key high performance processing on their SoCs (System on Chip), Imagination plays a key role in the semiconductor IP segment to deliver the levels of performance demanded by leading edge customers.
Says Tony King-Smith, VP marketing, Imagination: “Many of our licensees rely on TSMC to provide them with leading edge low power, high performance silicon foundry capabilities. This strengthening of our relationship with TSMC reflects our determination to deliver the best possible SoC solutions on the latest silicon processes for our SoC IP licensing partners. We believe this initiative will ensure that Imagination’s licensees to continue to push the boundaries of what is possible for future generations of advanced SoCs.”
Says Mark Dunn, VP of IMGWorks, Imagination’s SoC implementation group: “The characteristics of the latest processes such as 28HPM and beyond have to be taken increasingly into account when designing future high performance IP-based solutions. As major blocks such as GPUs increasingly dominate the area, power and performance of next generation SoCs, design flows need to be tuned to maintain the optimum balance between maximizing IP portability and achieving the best possible performance. We believe this extensive engineering partnership will greatly benefit all of our IP partners.”
“We are delighted to be working with Imagination to deliver the full benefits of TSMC’s latest and most advanced processes for mobile and embedded applications,” says Suk Lee, Senior Director of Design Infrastructure Marketing Division, TSMC.  “By leveraging Imagination’s leadership position in the market, we can help our customers to ship the most highly optimised SoCs.”

Imagination and TSMC Strengthen Technology Collaboration [press release, March 25, 2013]

TSMC optimising 16nm FinFET design flows using PowerVR GPUs to drive mobile performance
Kings Langley and Hsinchu – March 25, 2013 – TSMC (TWSE: 2330, NYSE: TSM) and Imagination Technologies (LSE: IMG.L), a leading multimedia, processor, communications and cloud technologies company, today announced the next phase of their technology collaboration.
As part of this new phase of their relationship, Imagination will work closely with TSMC to develop highly optimised reference design flows and silicon implementations using Imagination’s industry-leading PowerVR Series6 GPUs combined with TSMC’s advanced process technologies, including 16-nanometer (nm) FinFET process technology.
Imagination and TSMC R&D teams will also work together to create fully characterised reference system designs, utilizing high bandwidth memory standards and TSMC’s 3D IC technology capability to demonstrate new levels of system performance and capabilities while retaining all the essential characteristics of power, silicon area and small package footprint demanded by high volume mobile SoCs.
As GPUs increasingly dominate the area, power and performance of next generation SoCs and the options available to designers using advanced silicon processes become more complex, design flows and libraries need to be optimally tuned to enable design teams to achieve the best possible performance, power consumption and silicon area in ever more demanding timescales. To address these challenges, Imagination and TSMC are investigating how the characteristics of the latest processes, such as 16FinFET, influence the design of high performance IP-based SoCs.
Says Hossein Yassaie, CEO of Imagination: “Many of our licensees rely on TSMC to provide them with leading edge low power, high performance silicon foundry capabilities. Through advanced projects initiated under this partnership, Imagination and TSMC are working together to showcase how SoCs will transform the future of mobile and embedded products. We are delighted to announce our strengthening relationship with TSMC, and look forward to seeing the fruits of these projects benefiting our many mutual customers.”

“Just as memory drove silicon processes in the ‘80s and ‘90s, and CPUs drove processes further in the late ‘90s and ‘00s, high performance mobile GPUs for graphics and compute applications are one of the major drivers for our most advanced process technologies,” says Dr. Cliff Hou, TSMC Vice President, R&D. “We’re pleased to be working with Imagination, an established leader in mobile and embedded GPU IP, to understand how best to use PowerVR GPUs to work with us to optimize future generations of our most advanced process technologies, and advanced system design techniques.”

Imagination IP cores for next generation SoCs
Imagination is a member of TSMC’s Soft-IP Alliance program, through which it has begun to validate all of its major IP core families so that TSMC’s customers can take full advantage of the results of this collaboration. Imagination’s IP portfolio is unrivalled in its breadth, including:
• PowerVR GPU (graphics processor) Series5, 5XT and 6 (‘Rogue’): the most widely shipped for mobile and embedded graphics and GPU Compute
• PowerVR VPU (video processor) Series3 and 4: the industry’s most widely deployed range of multi-standard video decoder and encoder cores for applications from mobile to ultra-HD
• Ensigma RPU (radio processor) Series3 and 4: the multi-standard programmable communications and connectivity technology for TV, radio, Wi-Fi and Bluetooth
• MIPS CPU and embedded processors: advanced processor architectures featuring hardware multi-threading that deliver class-leading performance from high end Android-based applications processors down to small yet highly efficient embedded processors

Cadence and TSMC Strengthen Collaboration on Design Infrastructure for 16nm FinFET Process Technology [press release, April 8, 2013]

Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs – from design analysis through signoff – and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.
FinFETs help deliver the power, performance, and area (PPA) advantages that are needed to develop highly differentiated SoC designs at 16 nanometers and smaller process technologies. Unlike a planar FET, the FinFET employs a vertical fin-like structure protruding from the substrate with the gate wrapping around the sides and top of the fin, thereby producing transistors with low leakage currents and fast switching performance. This extended Cadence-TSMC collaboration will produce the design infrastructure that chip designers need for accurate electrical characteristics and parasitic models required for advanced FinFET designs for mobile and enterprise applications.
The FinFET device requires greater accuracy, from analysis through signoff, and that is why TSMC is teaming with Cadence on this project,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “This collaboration will enable designers to use the new process technology with confidence earlier than ever before, allowing our mutual customers to meet their power, performance and time-to-market goals.”
Producing the design infrastructure necessary for these types of complex, groundbreaking processes requires close collaboration between foundries and EDA technology innovators,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “In joining with TSMC, a leader in FinFET technology, Cadence brings unique technology innovations and expertise that will provide designers with the FinFET design capabilities they need to bring high-performance, power-efficient products to market.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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1 Comment

  1. […] ← TSMC’s 16nm FinFET process to be further optimised with Imagination’s PowerVR Ser… […]

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