This was said by Thomas Wong, director within strategic business operations at Cadence’s IP Group at the 52nd Design Automation Conference in June, 2015. Source: DAC 2015: How Best to Manage Third-Party IP Integration post of August 10, 2015 in The Fuller View blog for the Cadence community. This will—no doubt—strategically change the SoC landscape.
My next thought: Would it strategically change the semiconductor industry landscape? Particularly what has been described previously in China Fabless Semiconductor Panel: Don’t Pack Your Bags Just Yet post of June 18, 2014 in the Industry Insights blog for the Cadence community as:
The Chinese fabless semiconductor market is growing rapidly, there are over 600 fabless companies, and the Chinese government is (reportedly) gearing up for a major investment in semiconductors. However, many of those 600 companies are small and/or unprofitable, there’s a cultural bias against mergers and acquisitions, and only a small portion of the ICs consumed in China are actually manufactured there.
Watching the July 15, 2015 video Advanced Node Leadership (20nm, 16nm/14nm) and Summary from the Cadence Design Systems YouTube channel it seems to be the case. And not only with drastic changes that will happen in China (see the Digitimes Research: China looks at 70% IC self-sufficiency in 2025 report from August 28, 2015) but even more in India where Cadence is putting an equal emphasis on:
This video was starting the “Innovus launch seminar” there (in India).
As the next step one should understand what has been decsribed in my The (now) not so “secret sauce” behind ARM Cortex-A72 post yesterday. For a very good report on Innovus see as well the Cadence’s New Implementation System Promises Better TAT and PPA post of March 11, 2015 from SemiWiki.com.
The very close cooperation between Cadence and ARM on the advanced nodes like the 16nm FinFET has indeed been a major factor in this very new situation within the semiconductor industry. And the progress with other partners has been very significant since that:
INNovus, our next generation digital implementation system, continues to rapidly gain traction with market-shaping customers on their most advanced designs. Qualcomm Technologies, NVIDIA, ST Microelectronics, and Faraday Technology have joined ARM, Freescale, Juniper and others in adopting INNovus for production design at the most advanced nodes, benefitting from excellent quality of results and faster turnaround time.
This was the remark of Lip-Bu Tan, Cadence President and Chief Executive Officer, regarding that and published in CADENCE DESIGN SYSTEMS, INC. Second Quarter 2015 Financial Results Conference Call, July 27, 2015 document. Then in a separate report on the Q&A part published by Yahoo! he continued:
Clearly the customers see the benefit of the massive parallel architecture, faster runtime, five-time is significant and also the scale to 10 million instances, that is significant for them. We highlight some of the key names like Qualcomm Technology, Nvidia, STMicroelectronics, Faraday to join ARM, Freescale and Juniper. They are not just evaluating. Actually they are design — adopting our Innovus for production design for the most advanced node, based on the excellent quality of result and faster turnaround, and they are clearly seeing the benefit of the delivery that we mentioned earlier. Right now, we have a good design win, and now we are really focused on proliferating to various product groups, so that they can be comprehensively using us as the platform of choice.
then came a question about the future nodes:
Gus Richard, Northland Securities – Analyst 
Thanks. Thank you for that. Secondly when I look at some of the folks working on 10-nanometers, have announced that they will delay implementation, 7 and 5 look even more challenging. There’s been a slow down in the cadence of Moore’s Law. Can you talk a little bit about how that might affect your business in terms of new EDA tools, or will people pivot to other processes like FD-SOI that will give you a new opportunity? Again, how do you think that will affect the growth of the overall business?
Lip-Bu Tan, Cadence Design Systems, Inc. – President & CEO 
Very good question. Very insightful questions. I think a couple things. One, clearly we work closely with our customers and also our foundry partners, and we want to make sure that our tools are optimized for various process that our customer demand them. Clearly, 10-nanometer, some are slowing down, some are not slowing down. It really depends on some of the key applications they are driving.
Clearly on some of the mobile and some of the graphic and computer mission related areas, advanced node is critical. We will work very close with our customer and foundry on 10 and 7 nanometers. When you move down to 5 nanometers, clearly that patterning may not be enough. Then you’re starting to really look at the EUV.
For 5 nanometer, from my humble experience, it’s critical to have EUV, and I’m very pleased to see that [EFMAO], the EUV are making progress. They can go up to 80 watts now, and they can go up to 500 wafers per day. That is extremely encouraging. Then you starting to look at TSMC, Intel progress on the EUV side and also some of the photo-resist-related development. So we keep a very close eye on this whole road map and process technology, and we also work closely with the equipment, semiconductor equipment company, to make sure they are ready. And in terms of FD-SOI and the various version of the process, we work closely with our foundry partners, and that will be driven by customers. We work closely with the customer, understanding which process node, which foundry they are using. Our tool will be optimized, ready for them. That is our job.
With all that it is clear that the ARM partnership will be THE driving force for the smaller/emerging industry players in China and India as well. This is how that has been presented in ARM-Cadence Partnership Benefits to End Customer video recorded on the same “Innovus launch seminar” in India (from the same Cadence Design Systems YouTube channel, and made available there also on July 15, 2015):
According to the March 10, 2015 article Cadence Looks to Improve Position in Digital Design Tools from IHSElectronics360:
Cadence has long had the dominant analog design tool set in the EDA landscape. On the digital side, however, Cadence has lagged its larger rival, Synopsys Inc. The new physical implementation platform, dubbed Innovus, is Cadence’s attempt to bridge that gap.
“Cadence has always been known as an analog company,” said Anirudh Devgan, senior vice president of the Digital and Signoff group at Cadence. “The question on everyone’s mind is, ‘Can Cadence be best-in-class in digital?'”
While Cadence’s Encounter physical implementation system has roughly 40 percent market share, according to Devgan, it has for years trailed Synopsys’ IC Compiler product—especially among top 10 semiconductor vendors.
“We have very good market share, but we want to have much better share among the top 10,” Devgan said. “That’s where they are spending a lot of money.”
Devgan, who calls the Innovus launch the most significant for Cadence in the past five to 10 years, said the tool was built-in house by a team of engineers that has been augmented by between 90 and 100 people in recent months.
“Over the past two years, we have hired a lot of very smart people,” Devgan said. “This [launch of Innovus] is the result of that.”
And according to the July 14, 2015 article Lip-Bu Tan talks about the challenges and opportunities facing the EDA sector from New Electronics
The transition from a laggard to a leader in six years coincides with the tenure of Lip-Bu Tan, who was appointed the company’s president and CEO in 2009.
Over the last six years, Cadence has worked hard to reposition itself to meet the needs of a changing global market. Starting with the concept of EDA360, Cadence now offers what it describes as System Design Enablement.
“EDA360 was just that – a concept – but the disruption we identified then is with us today. It’s a reality. System providers have very big challenges to contend with and have different needs from the customers we traditionally worked with.
“Today, we offer hardware/software co-design and co-verification tools, as well as design and verification suites for high level abstractions as part of our integrated tool set,” Tan explains. “We are more application driven and need to be able to help companies look at the wider system, whether that is the IP, the power envelope, signal integrity or the PCB.”
Lip-Bu Tan has served as President and CEO of Cadence Design Systems since January 2009 and has been a member of the Cadence Board of Directors since February 2004. He also serves as chairman of Walden International, a venture capital firm he founded in 1987. Prior to founding Walden, Tan was Vice President at Chappell & Co. and held management positions at EDS Nuclear and ECHO Energy.
And regarding India you can find his thoughts here: In conversation with Lip Bu Tan, Chairman of Walden International [ETTech YouTube channel, Aug 19, 2015] Lip-Bu Tan, Chairman & founder of Walden international, talks about the firm’s plans for India and why he is bullish about the Indian semiconductor and hardware space.