The Dawn of the SoC 2.0 Era: The TSMC Perspective

From its companion post The Dawn of the SoC 2.0 Era: The ARM Perspective

futureICT - Cortex-A Roadmap Strategy -- April-2015

Source of the slide: ARM Cortex系列核心介绍 (Core ARM Cortex Series Introduction, 52RD, April 13, 2015)

Regarding TSMC itself the April 8 conclusion in TSMC Outlines 16nm, 10nm Plans article by EE|Times is:

“It’s not completely clear who is ahead at 16/14 but I think TSMC is making a major commitment to trying to be ahead at 10,” Jones said. “If that happens and TSMC has closed the gap with Intel, the issue is then if TSMC’s 10 and Intel’s 10 are the same,” he said.

Background from the April 14, 2015 TSMC Symposium: “10nm is Ready for Design Starts at This Moment” article in Cadence Communities Blog:

The 10nm semiconductor process node is no longer in the distant future – it is here today, according to presenters at the recent TSMC 2015 Technology Symposium in San Jose, California. TSMC executives noted that EDA tools have been certified, most of the IP is ready or close to ready, and risk production is expected to begin in the fourth quarter of 2015.

Here are some more details about 10nm at TSMC as presented in talks by Dr. Cliff Hou, vice president of R&D at TSMC (right), and Dr. BJ Woo, vice president of business development at TSMC (below left). At the TSMC Symposium, speakers also introduced two new process nodes, 16HHC and 28HPC+ (see blog post here).

According to Woo, TSMC is not only keeping up with Moore’s Law – it is running ahead of the law with its 10FF offering. “We have done a lot more aggressive scaling than Moore’s Law demands for our 10nm technology,” she said. A case in point is the fully functional 256Mb SRAM with a cell size that is approximately 50% smaller than the 16FF+ cell size. She called this an “exceptional shrink ratio” that goes beyond traditional scaling.

And it’s not just SRAM. The 10FF node, Woo said, can scale key pitches by more than 70%. Combine that with innovative layout, and 10nm can achieve almost 50% die size scaling compared to 16FF+. “And this is very, very aggressive,” she said.

After noting that the 16FF+ already provides “clear performance leadership,” Woo said that 10FF offers a 22% performance gain over 16FF+ at the same power, or more than 40% power reduction at the same speed. This comparison is based on a TSMC internal ring oscillator benchmark circuit. For the Cortex-A57 test chip used to validate EDA tools, the result was a 19% speed increase at the same power, and a 38% power reduction at the same speed.

New features in 10FF include a unidirectional (1D) layout style and new local interconnect layer. These features help 10FF achieve a 2.1X logic density improvement over 16FF+, whereas normally TSMC gets about a 1.9X density boost for node migration, Woo said. In addition to the density improvement, the 1D Mx architecture can reduce CD (critical dimension) variation by 60%, she said.

And an already remarkable quote from April 12, 2015 TSMC Symposium: New Low-Power Process, Expanded R&D Will Drive Vast Innovation: TSMC Executive article in Cadence Communities Blog:

Hock Tan, CEO of Avago, described a symbiotic relationship between TSMC and his company that led to a super high-density switch for a networking customer, implemented in 16FF+. The switch has 96 ports, each running 100G Gbps, and drawing less than 2W each. That enables, in a next-generation data center, the tripling of a switch performance to more than 10 Tbps.

Moreover, according to the April 12, 2015 TSMC Symposium: New 16FFC and 28HPC+ Processes Target “Mainstream” Designers and Internet of Things (IoT) article from Cadence Communities Blog:

16FFC is a “compact” version of the 16nm FinFET+ (16FF+) process technology that is now in risk production at TSMC. It claims advantages in power, performance, and area compared to the existing 16FF+ process, along with easy migration from 16FF+. It can be used for ultra low-power IoT applications such as wearables, mobile, and consumer.

28HPC+ is an improved version of the 28HPC (High Performance Compact) process, which is itself a fairly recent development. Late last year 28HPC went into volume production, and it provides a 10% smaller die size and 30% power reduction compared to TSMC’s earlier 28LP process. 28HPC+ ups the ante by providing 15% faster speed at the same leakage, or 30-50% reduction in leakage at the same speed, compared to 28HPC.

TSMC also provided updates on other processes on its roadmap, which includes the following:

  • High Performance – 28HP, 28HPM, 20SoC, 16FF+
  • Mainstream – 28LP, 28HPC, 28HPC+, 16FFC
  • Ultra Low Power – 55ULP, 40ULP, 28ULP, 16FFC (16FFC is in both mainstream and low power categories)

In connection with that remember the September 29, 2014 announcement:
TSMC Launches Ultra-Low Power Technology Platform for IoT and Wearable Device Applications

TSMC (TWSE: 2330, NYSE: TSM) today announced the foundry segment’s first and most comprehensive ultra-low power technology platform aimed at a wide range of applications for the rapidly evolving Internet of Things (IoT) and wearable device markets that require a wide spectrum of technologies to best serve these diverse applications. In this platform, TSMC offers multiple processes to provide significant power reduction benefits for IoT and wearable products and a comprehensive design ecosystem to accelerate time-to-market for customers.

TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.

Compared with their previous low power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life — by 2X to 10X — when much smaller batteries are demanded in IoT/wearable applications.

“This is the first time in the industry that we offer a comprehensive platform to meet the demands and innovation for the versatile Internet of Things market where ultra-low power and ubiquitous connectivity are most critical,” said TSMC President and Co-CEO, Dr. Mark Liu. “Bringing such a wide spectrum of offerings to this emerging market demonstrates TSMC’s technology leadership and commitment to bring great value to our customers and enable design wins with competitive products.”

One valuable advantage offered by TSMC’s ultra-low power technology platform is that customers can leverage TSMC’s existing IP ecosystem through the Open Innovation Platform®. Designers can easily re-use IPs and libraries built on TSMC’s low-power processes for new ultra-low power designs to boost first-silicon success rates and to achieve fast time-to-market product introduction. Some early design engagements with customers using 55ULP, 40ULP and 28ULP nodes are scheduled in 2014 and risk productions are planned in 2015.

“TSMC’s new ultra-low power process technology not only reduces power for always-on devices, but enables the integration of radios and FLASH delivering a significant performance and efficiency gain for next-generation intelligent products,” said Dr. Dipesh Patel, executive vice president and general manager, physical design group, ARM. “Through a collaborative partnership that leverages the energy-efficient ARM® Cortex®-M and Cortex-A CPUs and TSMC’s new process technology platform, we can collectively deliver the ingredients for innovation that will drive the next wave of IoT, wearable, and other connected technologies.”

“Low power is the number one priority for Internet-of-Things and battery-operated mobile devices,” said Martin Lund, Senior Vice President and General Manager of the IP Group at Cadence. “TSMC’s new ULP technology platform coupled with Cadence’s low-power mixed-signal design flow and extensive IP portfolio will better meet the unique always-on, low-power requirements of IoT and other power sensitive devices worldwide.”

CSR has an unequalled reputation in Bluetooth technology and has been instrumental in its progression, including helping to write the Bluetooth Smart standard that is meeting the demands of today’s rapidly evolving consumer electronics market,” said Joep van Beurden, CEO at CSR. “For many years, CSR has closely collaborated with TSMC, and we are pleased to demonstrate the results of that collaboration with the adoption of the 40ULP platform for our next generation of Bluetooth Smart devices including products for markets like smart home, lighting and wearables that are enabling the growth of the Internet of Things. Our solutions simplify complex customer challenges and help speed their time to market by allowing them to design and deliver breakthrough low power wireless connected products on these powerful new platforms.”

“The imaging SoC solutions of Fujitsu Semiconductor Limited bring the best balance between high imaging quality and low power consumption, to meet the significant demand from our customers and the electronics market,” said Tom Miyake, Corporate Vice President, at System LSI Company of Fujitsu Semiconductor Limited. “We welcome that TSMC is adding the 28ULP technology to its successful 28nm platform. We believe this technology will provide our SoCs with the key feature: low power consumption at low cost.”

Nordic Semiconductor has been a pioneer and leader in ultra-low power wireless solutions since 2002, and with the launch of its nRF51 Series of Systems-on-Chip (SoCs) in 2012 the company established itself as a leading vendor of Bluetooth Smart wireless technology,” said Svenn-Tore Larsen, CEO of Nordic Semiconductor. “We have been collaborating closely with TSMC on the selection of process technology for our upcoming nRF52 Series of ultra-low power RF SoCs. I am happy to announce that we have selected the TSMC 55ULP platform. This process is a key enabler for us to push the envelope on power consumption, performance and level of integration of the nRF52 Series to meet the future requirements of Wearable and Internet of Things applications.”

“Built on TSMC’s Ultra-Low Power technology platform and comprehensive design ecosystem, Realtek’s Bluetooth Energy Efficient smart SoC, BEE, supports the latest Bluetooth 4.1 specification featuring Bluetooth Low Energy (BLE) and GATT-based profiles,” said Realtek Vice President and Spokesman, Yee-Wei Huang. “BEE’s power efficient architecture, low power RF, and embedded Flash are ideal both for the IoT and for wearable devices such as smart watches, sport wristbands, smart home automation, remote controls, beacon devices, and wireless charging devices.”

Silicon Labs welcomes TSMC’s ultra-low power initiative because it will enable a range of energy-friendly processing, sensing and connectivity technologies we are actively developing for the Internet of Things,” said Tyson Tuttle, Chief Executive Officer, Silicon Labs. “We look forward to continuing our successful collaboration with TSMC to bring our solutions to market.”

“Synopsys is fully aligned with TSMC on providing designers with a broad portfolio of high-quality IP for TSMC’s ultra-low power process technology and the Internet of Things applications,” said John Koeter, Vice President of Marketing for IP and Prototyping at Synopsys. “Our wide range of silicon-proven DesignWare® interface, embedded memory, logic library, processor, analog and subsystem IP solutions are already optimized to help designers meet the power, energy and area requirements of wearable device SoCs, enabling them to quickly deliver products to the market.”

As well as the ARM and Cadence Expand Collaboration for IoT and Wearable Device Applications Targeting TSMC’s Ultra-Low Power Technology Platform announcement of Sept 29, 2015:

ARM® and Cadence® today announced an expanded collaboration for IoT and wearable devices targeting TSMC’s ultra-low power technology platform. The collaboration will enable the rapid development of IoT and wearable devices by optimizing the system integration of ARM IP and Cadence’s integrated flow for mixed-signal design and verification, and their leading low-power design and verification flow.

The partnership will deliver reference designs and physical design knowledge to integrate ARM Cortex® processors, ARM CoreLink™ system IP, and ARM Artisan® physical IP along with RF/analog/mixed-signal IP and embedded flash in the Virtuoso®-VDI Mixed-Signal Open Access integrated flow for the new TSMC process technology offerings of 55ULP, 40ULP and 28ULP.

“TSMC’s new ULP technology platform is an important development in addressing the IoT’s low-power requirements,” stated Nimish Modi, senior vice president of Marketing and Business Development at Cadence. “Cadence’s low-power expertise and leadership in mixed-signal design and verification form the most complete solution for implementing IoT applications. These flows, optimized for ARM’s Cortex-M processors including the new Cortex-M7, will enable designers to develop and deliver new and creative IoT applications that take maximum advantage of ULP technologies.”

“The reduction in leakage of TSMC’s new ULP technology platform combined with the proven power-efficiency of Cortex-M processors will enable a vast range of devices to operate in ultra energy-constrained environments,” said Richard York, vice president of embedded segment marketing, ARM. “Our collaboration with Cadence enables designers to continue developing the most innovative IoT devices in the market.”

This new collaboration builds on existing multi-year programs to optimize performance, power and area (PPA) via Cadence’s digital, mixed-signal and verification flows and complementary IP alongside ARM Cortex-A processors and ARM POP™ IP targeting TSMC 40nm, 28nm, and 16nm FinFET process technologies. Similarly, the companies have been optimizing the solution based around the Cortex-M processors in mixed-signal SoCs targeting TSMC 65/55nm and larger geometry nodes. The joint Cortex-M7 Reference Methodology for TSMC 40LP is the latest example of this collaboration.

For the above keep in mind The TSMC Grand Alliance [TSMC, Dec 3, 2013]:

The TSMC Grand Alliance is one of the most powerful force for innovation in the semiconductor industry, bringing together our customers, EDA partners, IP partners, and key equipment and materials suppliers at a new, higher level of collaboration.

The objectives of the TSMC Grand Alliance are straightforward: to help our customers, the alliance members and ourselves win business and stay competitive.

We know collaboration works. We have seen it in the great strides our customers and ecosystem members have made through the Open Innovation Platform® where today there are 5,000 qualified IP macros and over 100 EDA tools that supports our customers’ innovation and helps them attain maximum value from TSMC’s technology.

Today Open Innovation Platform is an unmatchable design ecosystem and a key part of the Grand Alliance that will prove much more powerful. Looking at R&D investment alone, we calculate that TSMC and ten of our customers invest more in R&D than the top two semiconductor IDMs combined.

Through the Grand Alliance TSMC will relentlessly pursue our mission and collaborate with customers and partners. We need each other to be competitive. We need each other to win. Such is the power of the Grand Alliance.

[Some more information is in the very end of this post]

A related overview in Kicking off #ARMWearablesWK with an analysts view of the market post of November 17, 2014 of ARM Connected Community blog by David Blaza:

Today as we kickoff ARM Wearables Week we hear from Shane Walker of IHS who is their Wearables and Medical market expert.

Shane’s take on this market is that it’s for real this time (there was a brief Smartwatch wave a few years ago) and will continue to be a hot growth sector through 2015. One of the great benefits of talking with analysts like Shane is they help you think through what’s going on and bust a few myths that may have found their way into our thinking. For example I asked Shane what the barriers to growth were and he carefully and patiently pointed out that Wearables are growing at a 21% CAGR already and will hit $12b in device sales this year (without services, more on that later in the week).  So this is not an emerging or promising market, it’s here and growing at an impressive rate. By 2019 Shane’s estimate is that it will hit $33.5b in device sales and services are increasingly going to factor into the wearables experience (Big Data is coming!).

Shane breaks the Wearables market down to 5 major categories:

  1. Healthcare and Medical
  2. Fitness and Wellness
  3. Infotainment
  4. Industrial
  5. Military

I’m glad he did this for me because wearables are incredibly diverse and this week you are going to see some category defying products here such as smart Jewelry where does that fit?

Below you can see a table chart that Shane was willing to share that shows his estimate for market size and units sold, the main learning for me is how much of this market is healthcare related. Also attached below are details on what services IHS offer in the Wearables market or you can find them here.

futureICT - World Market for Wearable Technology - Revenue by Application -- IHS-November-2014

attached is: Wearable Technology Intelligence Service 2014.pdf  [IHS Technology, November 17, 2014]

Note the following table in that:
futureICT - Wearable Technology Data Coverage Areas by IHS

More information:
– A Guide to the $32b Wearables Market [IHS Technology, March 11, 2015]
– which has a free to download whitepaper:
Wearable Technology: The Small Revolutions is Making Big Waves

Brief retrospective on the SoC 1.0 Era

futureICT - Shipments of TSMC Advanced Technologies Q1'2009 - Q1'2015

Detailed Background from TSMC’s quaterly calls

Q1 2015:

Mark Liu – TSMC – President & Co-CEO
[update on new technology]

The continuous demand of more functionality and integration in smartphones drives for more silicon content. We expect smartphones will continue to drive our growth in the next several years.

In the meantime, we see IoT appears us — present us new growth opportunities. The proliferation of IoT not only will bring us growth in the sensor, connectivity and advanced packaging areas, the associated application and services, such as big data analytics, will also further our growth in the computation space, including application processor, network processor, image processor, graphic processor, microcontroller and other various processors. That was the long-term outlook.

I’ll update some of our 10-nanometer development progress. Our 10-nanometer technology development is progressing well. Our technology qualification remains in Q4 this year.

Recently we have successfully achieved fully functional yields of our 256-megabit SRAM. Currently we have more than 10 customers fully engaged with us on 10-nanometer. We still expect to have 10-nanometer volume ramp in fourth quarter 2016 and to contribute billing in early 2017.

This technology adopts our third-generation FinFET transistor and have scaling more than one generation. Its price is fully justified by its value for various applications, including application processor, baseband SoC, network processor, CPU and graphic processors. Its cost and price ratio will comply to our structural profitability considerations.

As for new technology development at TSMC, I’d like to start with — to update you our 7-nanometer development. We have started our 7-nanometer technology development program early last year. We also have rolled out our 7-nanometer design and technology collaboration activity with several of our major customers. Our 7-nanometer technology developments today are well in progress.

TSMC’s 7-nanometer technology will leverage most of the tools used in 10-nanometer, in the meantime achieve a new generation of technology value to our customers. The 7-nanometer technology risk production date is targeted at early 2017.

Now I would like to give you an update on EUV. We have been making steady progress on EUV. Both our development tools, we have two NXE 3300 have been upgraded to the configuration of 80 watt of EUV power, with an average wafer throughput of a few hundred wafers per day. We continue to work with ASML to improve tool stability and availability. We also are working with ASML and our partners on developing the infrastructure of EUV, such as masks and resists.

Although today the process on record of both 10-nanometers and 7-nanometer are on immersion tools, with innovative multiple patterning techniques, we will continue to look for opportunity to further reduce the wafer cost and simplify the process flow by inserting EUV layer in the process.

Now I’d like to give you an update of our recently announced ultra-low-power technologies. We have offered the industry’s most comprehensive ultra-low-power technology portfolio, ranging from 55-nanometer ULP, 40-nanometer ULP, 28-nanometer ULP, to the recently announced 16 FFC, a compact version of 16 FinFET Plus, enable continual reduction of operating voltage and power consumption. Today more than 30 product tape-outs planned in 2015 from more than 25 customers.

This 55- and 40-nanometer ULP will be the most cost-effective solution for low- to mid-performance wearable and IoT devices. The 28 ULP and 16 FFC will be the most power-efficient solution for high-performance IoT applications. In particular, our 16 FFC offers the ultra-low-power operation at a supply voltage of 0.55 volts, with higher performance than all of the FD-SOI technologies marketed today.

Lastly I’ll give you an update of our recent IoT specialty technology development. We have developed the world’s first 1.0-micron pixel size 16-megapixel CMOS image sensor, with stacked image signal processor, which was announced in March by our customer for the next-generation smartphone. Secondly, we continue to drive the best low resistance in BCD [Bipolar-CMOS-DMOS for DC-to-DC converter: together with Ultra-High-Voltage (UHV) technology for AC-to-DC converter—are the key to enable monolithic integrated PMIC design] technology roadmap, from 0.18 micron to 0.13 micron and from 8-inch to 12-inch production for wireless charging and fast wired charging of mobile devices. We continue to extend our 0.13 BCD technology from consumer and industrial applications to automotive-grade electrical system control applications.

Lastly, recently we have started production in foundry’s first 40-nanometer industrial embedded Flash technology that was started from November last year. And this technology recently passed automotive-grade qualification, that was in March, for engine control applications.

C.C. Wei – TSMC – President & Co-CEO

I will update you the 28-nanometer, 20 and 16 FinFET status and also our InFO business.

First, 28-nanometer. This is the fifth year since TSMC’s 28-nanometer entered mass production. 28-nanometer has been a very large and successful node for us. Our market segment share at this node has held up well and is in the mid-70s this year. We expect this to continue in year 2016. In comparison, this is better than what we had in the 40-nanometer node.

The demand for 28-nanometer is expected to grow this year due to the growth of mid- and low-end smartphones and as well as the second-wave segment, such as radio frequency, circuit product and the Flash controllers that migrate into this node.

However, due to some customers’ inventory adjustments, which we believe is only going to be for the short term, the demand for 28-nanometer in the second quarter will be lower than our previous quarter, resulting in 28-nanometer capacity utilization rate to be in the high-80s range. But we expect the utilization rate of the 28-nanometer to recover soon and to be above 90% in the second half of this year.

While we are in the mass production, we also continue to improve the performance of our technology. Last year we have introduced our 28-HPC, which is a compact version of 28-HPM. For the purpose of helping 64-bit CPU conversion for mid- to low-end market, this year we further improved the 28-HPC to 28-HPC Plus. For comparison, 28-HPC Plus will have 18% power consumption — lower power consumption at the same speed or 15% faster speed at the same kind of power.

As for the competitive position, we are confident that we will continue to lead in performance and yield. So far we do not see there is a very much effective capacity in High K metal gate at 28-nanometer outside TSMC. And since we have already shipped more than 3m 12-inch 28-nanometer wafers, the learning curve has given us an absolute advantage in cost.

Now let me move to our 20 SoC. TSMC remains the sole solution provider in foundry industry for 20-nanometer process. Our yield has been consistently good after a very successful ramp last year. But recently we have observed customers’ planned schedule for product migration from 20 nanometer to 16 FinFET started sooner than we forecasted three months ago.

As a result, even we continue to grow 20-nanometer business in the second quarter of this year, our earlier forecast of 20-nanometer contributing above 20% of total wafer revenue this year has to be revised down by a few points to a level about the mid teens. That being the case, we still forecast the revenue from 20-nanometer will more than double that of year 2014’s level.

Now 16 FinFET. The schedule for 16 FinFET high-volume production remains unchanged. We will begin ramping in the third quarter this year. And the ramp rate appeared be faster than we forecasted three months ago, thanks to the excellent yield learning that we can leverage our 20-nanometer experience and also due to a faster migration from 20-nanometer to 16 FinFET.

In addition to good yield, our 16 FinFET device performance also met all products’ specs due to our very good transistor engineering. So we believe our 16 FinFET will be a very long-life node due to its good performance and the right cost. This is very similar to our 28-nanometer node.

We are highly confident that our 16 FinFET is very competitive. As we’ve said repeatedly, combining 20-nanometer and 16-nanometer, we will have the largest foundry share in year 2015. And if we only look at 16-nanometer alone, we still can say TSMC will have the largest 16- or 14-nanometer foundry share in year 2016.

Now let me move to our InFO business update. The schedule to ramp up the InFO in second quarter next year remains unchanged. We expect InFO will contribute more than $100m quarterly revenue by next year, fourth quarter next year, when it will be fully ramped.

Right now we are building a new facility in Longtan, that’s a city very near to Hsinchu, where our headquarters are, for ramping up InFO. Today a small product line is almost complete and it’s ready for early engineering experiment. This pilot line will be expanded to accommodate the high-volume ramp in year 2016.

Andrew Lu – Barclays – Analyst

… I think Mark presented at the Technology Symposium in San Jose mentioned that 16 FinFET versus competing technology is about 10% performance better. So can you elaborate what’s 10% performance better? If our die size is larger than our competitors, how can we get the 10% performance better?

Mark Liu – TSMC – President & Co-CEO

In the conference we talked about 16 FinFET Plus. That is our second-generation FinFET transistor. In that we improved our transistor performance a great deal. According to our information, that transistor speed, talk about speed at fixed power, is higher than the competitor by 10%. That’s what I meant. …  Because of the transistor structure, transistor engineering.

Andrew Lu – Barclays – Analyst

Compared to competing — is the competing the current competitor’s solution or the next-generation competitor’s solution? For example, LPE versus LPP or something like that?
Mark Liu – TSMC – President & Co-CEO
The fastest one. The fastest.
Andrew Lu – Barclays – Analyst
Their best one?
Mark Liu – TSMC – President & Co-CEO
Yes.

Dan Heyler – BofA Merrill Lynch – Analyst

My second question is relating to 20-nanometer. Here you certainly have a lot of growth in 16, with customers taping out aggressively, especially next year. Given your high share at 28, how do you keep 28 full? You obviously have a lot of technology there. Customers will move forward.

So I’m wondering, could you elaborate on new areas that are actually creating new demand at 28, such that you can continue to grow 28 next year. And do you think you can grow? I think previously you said maybe hold it at current levels even with 16 growing. So just maybe revisit that question.

C.C. Wei – TSMC – President & Co-CEO

To answer the question, I think the high-end smartphone will move to 16 FinFET. However, the mid- to — and lower-end smartphones will stay in the 28-nanometer because that’s very cost effective. And mid- and low-end smartphone continues to grow significantly. So that will give a very strong demand on 28-nanometer. In addition, we still have a second-wave product, like RF and Flash controller, as I use as an example, move into 28-nanometer.

So summing it up, I think the 28-nanometer’s demand continue to grow while we move into the 16 FinFET for high-end smartphone.

Michael Chou – Deutsche Bank – Analyst

As Mark has highlighted your EUV program, Does that imply you may consider using EUV in the second stage of your 16-nanometer — 10-nanometer ramp-up, potentially in 2018 or 2019? 

Mark Liu – TSMC – President & Co-CEO

Yes, we always look for opportunity to insert EUV in both 10-nanometer and 7-nanometer. The EUV technology provides not only some cost benefit, but also simplify the process. That means you can replace multiple layers with one layer that helps your yield improvement. So there’s opportunity both in quality and cost always exist so long as EUV’s productivity comes to the threshold point.

And in — as you noticed on 10-nanometer, our capacity build will largely done in 2016 and 2017. So 2018 will be inserted, if inserted, will be combined with some other tools upgrade, some tool upgrade to 7, for example, and replaced by the EUV tools. In that node it will not be a fresh capacity build with EUV at that time because that’s a little bit late in the schedule for the 10.

7-nanometer, of course it will be higher probability adopting EUV. And the benefit will be bigger because the 7-nanometer has a lot of multiple layers, quadruple, even multiple patterning layers, thus EUV can be more effective in reducing the cost and improve the yield, for example. So that’s our current status.

But today EUV is still in the engineering mode. The productivity, as you heard, will still have some gaps for practical insertion of the technology. So we’re still working on that, in that mode. And we have — although we have one-day performance up to 1,000 wafer per day, but I was talking about average still a few hundreds. And we need to get to more than 1,000 to consider a schedule to put it into the production.

Randy Abrams – Credit Suisse – Analyst

As you go to fourth quarter, how broad is the customer base? Is it a single key product or are you seeing broadening out of 16 FinFET as you ramp that in fourth quarter?

Mark Liu – TSMC – President & Co-CEO

… As for the second half, we think, first of all, the inventory adjustment will largely complete towards the end of second quarter.

We think the end market of smartphone is still healthy growth this year. Therefore the second half will resume the growth. And, more importantly, our 16 FinFET technology will start to ramp in the second half. So that will contribute a lot of growth, more than the 20-nanometer shipment reduction. So those two factors.

Roland Shu – Citigroup – Analyst

My first question is on given the fast ramp of 16-nanometer, so are we going to see meaningful revenue contribution for 16 in 3Q?

C.C. Wei – TSMC – President & Co-CEO

We ramp up in third quarter this year, but it’s many layers of process, plus about one month is back-end. So in 3Q we expect just the revenue just very minimum.

Bill Lu – Morgan Stanley – Analyst

This is a follow-up to Randy’s question. But I’m going to go over some numbers with you first before I ask the question, which is we did the math. I don’t think these are exactly right. But over the last five years we’ve got IDM zero growth, fabless 8%, but system houses above 20%, right. So system houses, I’m excluding memory, just the system LSI, the logic portion. I think that might be slightly conservative.

Now that’s a pretty big change. And I’m wondering how you should think about that, how you should — if you look at TSMC addressing the system houses versus the fabless customers, if you look at, for example, your market share, if you look at your margin for the system houses versus the fabless, how do you think about that?

Mark Liu – TSMC – President & Co-CEO

Yes. Indeed, in the past five years the system houses sourcing and foundry business to us has a much higher growth rate, as you quoted. But remember, that came from a very small base. Okay? But we welcome system house sourcing because we consider them are fabless too, fabless companies, the companies without fabs, bring business to us.

It’s not necessarily the margin has to do with what type of company sourced. It has to do with our value to that company and also the size, the size of the business. If the business is bigger, of course the — we probably can enjoy a slightly — a little bit better price. So it depends on the size of the business, less dependent on what company, system company or non-system company’s business.

Steven Pelayo – HSBC – Analyst

For the last three years or so, TSMC’s been growing 20%, 30% year-on-year revenue growth rates. First quarter 50% year on year. But to Bill’s question there, it does look like in the second half of the year, if I play around with your full-year guidance and what you’re doing, low single-digit year-on-year growth rates. And if we exclude maybe 16-nanometer, above 16-nanometer, maybe it’s flat to down. Is that the new industry? What are we talking now for industry growth rates for both the semi industry and in the foundry market this year?

90 days ago you suggested the semi market was going to grow 5% this year with foundries growing 12%. In light of your new guidance, in light of what it looks like you’re going to have very slight year-on-year growth rates in the second half of the year, what do you think that means for the overall industry?

Mark Liu – TSMC – President & Co-CEO

We think the semiconductor growth this year currently is indeed we adjusted down from 5% earlier to 4% at this time. Yes. We think it’s really due to the macroeconomic situation around the world today. And therefore the foundry market — foundry growth rate will adjusted down too. We are looking at about 10% range. So that’s why we revised our view on the current semiconductor growth.

Brett Simpson – Arete Research – Analyst

My question on 10-nanometer, I know it’s still 18 months away from ramp-up, but can you talk about how fast this ramp might scale relative to 20-nanometer or 28-nanometer?

And as you ramp up 10-nanometer for high-end smartphones, would you expect low-end smartphones to start migration from 28 with 16 FinFET in 2017?
Elizabeth Sun – TSMC – Director of Corporate Communications
… Your question seems to say that if we ramp 10-nanometer in the future, which will be targeting the high-end smartphone, will the low-end smartphone be migrating from 28-nanometer into 16-nanometers.
Brett Simpson – Arete Research – Analyst
And  just to add to that, Elizabeth, how quickly will 10-nanometer scale up relative to the scaling of 20-nanometer — the ramp-up of 20-nanometer and 28? Will it be as fast?
Elizabeth Sun – TSMC – Director of Corporate Communications
So the profile of the 10-nanometer ramp, will that be steeper than the profile of the 20 or the 28-nanometer?

Mark Liu – TSMC – President & Co-CEO

Okay. The first part of the question has to do with 10-nanometer ramp for the high-end smartphone, will the mid/low-end move to 16? I think we — this is up to our customers’ product portfolio. We definitely know a lot of customer is looking at 28-nanometer to use — to do as the low end. But the specification, the smartphone processor specification changes constantly. So what portion of that product will move to 16-nanometer? We think definitely there are some portion, but how a big portion really depends on their product strategy.

On the 10-nanometer ramp, I wouldn’t say it’s bigger. But at least it’s similar scale of our ramp as we do in 16 and as we do in 20.

Brett Simpson – Arete Research – Analyst Great.

Thank you. And let me just have a follow-up here. There’s been a lot of talk in the industry about one of your larger customers [Qualcomm] planning to introduce a new application processor on both Samsung’s 14-nanometer process as well as your 16 FinFET for the same chip later this year. And we haven’t really seen a single chip get taped out on two new processors at the same time before in the industry. So my question, how does this really work between the two foundries? Does it mean that that one customer can adjust dynamically, month to month, how they allocate wafers between you and Samsung? Or am I — or how might this work?
Elizabeth Sun – TSMC – Director of Corporate Communications … So your question seems to say that there is a customer that appeared to be working with two different foundries on the 14 and 16-nanometer node. And the products are about to arrive. You would like to understand how this customer will be allocating month by month the — what’s the production or the orders with both of the two foundries. Is that your question?
Brett Simpson – Arete Research – Analyst
Yes, that’s right. Whether they can move around dynamically how they allocate wafers. That’s right.

C.C. Wei – TSMC – President & Co-CEO

Well my answer is very typical. Our 16 FinFET is really very competitive. And we did not know that customer going to — how they’re going to allocate. I cannot even make any comment on that.

Gokul Hariharan – JPMorgan – Analyst

First of all on 16-nanometer, since Dr. Wei mentioned that next year a lot of demand on entry-level to mid-end smartphone is still going to stay at 28-nanometer, could you talk about your visibility for second-wave demand for 16-nanometer? 

What is the visibility that you have? Is it going to be really strong? Because you mentioned that a lot of the cost-sensitive customers would still stay on 28, at least for next year.

C.C. Wei – TSMC – President & Co-CEO

For 28-nanometer I said mid to low end this year that, and next year probably, that smartphone will stay in 28-nanometer because it’s very cost-effective and performance-wise is very good. For 16 FinFET I think that people will start to move with their product plan and some of the mid-end smartphone will move into 16-nanometer. That’s for sure.

In addition to that, we also see improving our 16 FinFET ultra-lower-power Mark just mentioned. And that will have a lot of application. And every product, lower power consumption is one of that advantage.

And so that would be our second wave of 16 FinFET.

Dan Heyler – BofA Merrill Lynch – Analyst

… So on 16, this FinFET Compact which is getting introduced, when would we expect to see that in volume production?

C.C. Wei – TSMC – President & Co-CEO

FFC? That will be ready next year. And we expect that high-volume production starts probably two years later. That’s year 2017. 2018 will reach the high volume.

Dan Heyler – BofA Merrill Lynch – Analyst

Okay. So is there a — so the cost-down version for mid-end phones FinFET that you alluded to, plus low power, when is that available?

C.C. Wei – TSMC – President & Co-CEO

Probably in 2017 second half.

Q4’2014:

Lora Ho – Taiwan Semiconductor Manufacturing Company Ltd – SVP and CFO

During the fourth quarter, the strong 20-nanometer ramp was mainly driven by communication-related applications. As a result, communication grew 18% sequentially and the revenue contribution increased from 59% in the third quarter to 65% in the fourth quarter. As for other applications, computer grew 7%, while consumer and industrial declined 21% and 11% respectively.

On a full-year basis, communication increased 39% and represented 59% of our revenue. The major contributing segments included baseband, application processors, image processors and display drivers. Another fast-growing application in 2014 was industrial and standard, which grew 30% year over year. The growth was mainly driven by increasing usage of power management ICs, near-field communications and audio codec within the mobile devices.

By technology, 20-nanometer revenue contribution started with a very small number in the second quarter, jumped to 9% in the third quarter and reached 21% in the fourth quarter. Such unprecedented ramp cannot be achieved without seamless teamwork with our customer, the R&D and operational people in TSMC.

On a full-year basis, 20 nanometer accounted for about 9% of our full-year wafer revenue. Looking forward, we are confident that 20 nanometer will continue its momentum to contribute 20% of the revenue for the whole year 2015.

Meanwhile, customer demand for our 28-nanometer wafers remained strong. Accordingly, these two advanced technologies, 20 nanometer plus 28 nanometer, represented 51% of our fourth-quarter total wafer revenue, a big increase from 43% in the third quarter.

Mark Liu – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO

Now I’ll give you a few words on 10-nanometer development update. Our 10-nanometer technology development is progressing and our qualification schedule at the end of 2015, end of this year, remains the same. We are now working with customers for their product tape-outs. We expect its volume production in 2017.

On the new technology development in TSMC, I’ll begin with beyond 10 nanometer I just talked about. We are now working on our future-generation platform technology development, with separate dedicated R&D development teams. These technologies will be offered in the 2017-to-2019 period. We are committed to push forward our technology envelope along the silicon scaling path.

In addition to the silicon device scaling, we are also working on the system scaling through advanced packaging to increase system bandwidth, to decrease power consumption and device form factors. Our first-generation InFO technology has been qualified. Currently we are qualifying customer InFO products with 16-nanometer technology. And it will be ready for volume ramp next year, 2016. We are now working on our second-generation InFO technology to supplement the silicon scaling of 10-nanometer generation.

On the other side, in addition to the recently announced 55ULP ultra-low power technology, 40ULP, 28ULP technologies for ultra-low power application, such as wearable and IoT, we are also working on 16ULP technology development. This 16ULP design kit will be available in June this year. It will be just suitable for both high-performance and ultra-low power or ultra-low voltage, less than 0.6-volt applications.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO

Good afternoon, ladies and gentlemen. I’ll update you on 28, 20, 16-nanometer status and the InFO business.

First on 28 nanometer. Since year 2011, we started to ramp up 28-nanometer production. Up to now we have enjoyed a big success in terms of a good manufacturing result and, most importantly, the strong demand from our customers. This year we expect the success will continue.

Let me give a little bit more detail, first on the demand side. The demand continues to grow, which are driven by the strong growth of mid- and low-end 4G smartphones, as well as the technology migration from some second-wave segments, such as the radio frequency, hard disk drive, flash controller, connectivity and digital consumers.

Second, on the technology improvement, we continue our effort to enhance 28-nanometer technology by improving the speed performance while reducing the power consumption. 28HPC, 28 ultra-low power technology are some examples.

So to conclude the 28-nanometer status, we believe we can defend our segment share well because of excellent performance and performance/cost ratio and our superior defect density results.

Let’s talk about the 20 SoC business status. After successfully ramp up in high volume last year, we expect to grow 20-nanometer business more than double this year due to high-end mobile device demand, which were generated by our customers’ very competitive products. Our forecast of the 20-nanometer business, as Lora just pointed out, will contribute 20% of the total wafer revenue. That remains unchanged.

Now on 16-nanometer ramp-up. We expect to have more than 50 product tape-outs this year on 16-nanometer. High-volume production will start in third quarter, with meaningful revenue contribution starting in fourth quarter this year. In order to stress again what our Chairman already mentioned, that combining 20 nanometer and 16 nanometer we expect to enjoy overwhelming market segment share.

Last, I will update on the InFO business. The traction on InFO is strong. We have engaged with many customers. And a few of these customers are expected to ramp up in second quarter next year. Right now we are building a small pilot line in a new site to prepare for high-volume production next year. Also we expect this InFO technology will contribute sizeable revenue in 2016.

Dan Heyler – BofA Merrill Lynch – Analyst

…. I guess as we look at your pie chart on your slide with communications and computer being amazingly only 9% of your revenue, and, say, 10 years ago that chart was much, much different, with computer being the biggest. As we look at computer opportunities going forward, I think to some extent there’s maybe a sense of a little bit of disappointment in that we don’t see ARM necessarily in PCs yet. We haven’t really necessarily seen that ecosystem come through in the server business. And big data being such an important trend going forward, with compute growing about 15% per year, I’m wondering what TSMC is doing or what your view of that opportunity will be in the future as a potential growth driver.

Morris Chang – Taiwan Semiconductor Manufacturing Company Ltd – Chairman

Server is one of them, Mark. Well there’s IoT actually also, and just don’t forget that mobile actually we think has a few more years to run yet. Really the TSMC silicon content in the average phone is actually increasing, which is something that is not recognized by a lot of people, because everybody says that the weight, the gravity is shifting to the middle level, lower-level priced phones. But according to our data, and we have kept track of it for quite a long time, the average of TSMC silicon content in the average phone is actually increasing.

So — and look, we still look for over — I think the number we have is that by 2019 there’ll be 2b phones manufactured. It is — I think last year it was, what, 1.3b? I think, yes, 1.3b. 1.3b to 2b. And, well, and the average TSMC silicon content per phone is increasing. And the number of phones is going up. So that’s by no means a — it’s still there. It’s still a growth engine.

And then IoT, I think we talked about IoT before, and now we are certainly not oblivious to the server possibility. So why don’t I ask Mark to talk about the server and maybe C.C. will talk a little about the IoT.

Mark Liu – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO

Okay, Dan. I’ll just respond to you on the server part. Chairman talked about the area we’re mostly focused on, phone, today. And that would drive — give us growth momentum in the next several years.

On server, we work with the product innovators around the world. And such a field definitely we’ll not lose in our radar screen and theirs. And TSMC has been, over the years, developed our technology to suit for high-power computing.

And from 65, 40, 28 to 16 nanometer, we continuously improve our transistor performance. And today we believe our 16 FinFET Plus transistor performance probably is the top of — is one of the top of the world. It’s well suitable, well capable of doing the computing tasks.

And actually before server, and there are several supercomputers around the world, in US and in Japan, already powered by our technology, doing the weather forecasting, whether the geo exploration applications today. And on the server, on ARM in particular, we have very close partnership with ARM in recent years. And ARM is a very innovative company. They produce CPU core and new architecture every year. And we reached our leading-edge technology very early with ARM and to design their leading-edge CPU cores. And that will continue and several of our customers are taking advantage of that.

Yes, in the past it’s been getting into slower as expected. That’s because the software ecosystem is slower to come. And — but actually a lot of the server companies, system company is continuing investing in this ecosystem. Linux-based ecosystem is coming very strong too. So I think the trend will continue. And we will, with our customers, get into these segments in the next — in the near future. Yes.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO

For the IoT, that would be a big topic right now in the whole industry. All I want to say is that we are happy to share with you that, a long time ago, we already focused on our specialty technology, which are the CMOS image sensor, MEMs, embedded Flash, all those kind of things. Today we add another new technology, ultra-low power, into it. And that will be the basis for the IoT technology necessary in the future. We believe that when the time comes and IoT business becomes big, TSMC will be in a very good position to capture most of the business. That’s what I share with you. Thank you.

Randy Abrams – Credit Suisse – Analyst

… And the follow-up question on profitability. If you could give a flavor on structural profitability for 2015 and some of the flavor for 20, how quick that may get to corporate margins, and for 16, because it’s an extension, whether that could be near corporate margins as that comes up. And if you could give a comment on the inventory at current levels, if there’s any — if that will stay at these higher levels from the WIP you’ve been building or if that may come back down to a different level.

Lora Ho – Taiwan Semiconductor Manufacturing Company Ltd – SVP and CFO

Randy, you have multiple questions. I recall you asked for the structural profitability. That’s you first question, right? From what we can see now, we are quite confident we can maintain equal or slightly better structural profitability, standard gross margin versus 2014.

For the 20-nanometer and 16-nanometer ramping, how would that affect corporate margin? I have said in last July it usually takes seven or eight quarters for any new leading-edge technology to get close to the corporate average. So for 20 nanometer, it will take eight quarters. So we believe — so 20 nanometer start to sell in second quarter 2014, and we expect by first quarter 2016, that’s eight quarters, it will be at corporate average level.

For 16, we are going to mass produce this product. It will follow the similar trend. 16 nanometer will be based on the feature of 20 nanometer, so the margin will start to be higher. But it will also follow the similar trend. It takes seven quarters to reach to corporate average. So say we plan to mass produce 16 FinFET in third quarter 2015, so by first quarter 2017 you will get close to corporate average. So there will — before that there will be still small dilutions. For this year, the dilution will be 2 to 3 percentage points. And the last year, the second half will be 3 to 4 percentage points and very low in 2016.

Donald Lu – Goldman Sachs – Analyst

… Chairman, about six months ago you gave us a comment on your estimate on TSMC’s market share in FinFET in 2015, 2016, 2017. So has that changed?

Morris Chang – Taiwan Semiconductor Manufacturing Company Ltd – Chairman

… Donald’s question was I said — actually I looked up my statement at that time, July 16 of last year. I said on the subject of 16 and 20, 16-nanometer and 20-nanometer technology, I said that — I actually made three statements.

The first statement was that because we started 16 a little late, our market share in 2015, our 16-nanometer market share in 2015 will be smaller than our major largest competitor’s.

The second statement I made was that we started 16 late because we wanted to do 20. And so if you combine 20 and 16, our major competitor, who will be slightly ahead of us this year on the 16, he has very little 20. Almost no 20 at all. And if we combine 20 and 16, our combined share in this year will be much higher than that competitor’s.

The third statement I made is that in 2016 we will have much larger share in just 16 nanometer than that competitor.

All right. First I want to say that I, at this time, stand on those statements. In fact, I now will add a couple of statements. The statements I will add are — that’s fourth statement now. Okay? When we have a larger share of just 16 alone in 2016, the 16 market will also be much larger than this year, 2015. So, yes, we’re slightly behind. We have a smaller market share in 2015 in a smaller market. Next year we will have a larger share, in fact much larger share, in a much larger market, 16.

So — and another statement I want to make is that I’m, at this point, very, very comfortable with all those statements that I have made on July 16 last year and the statements that I have added today. I’m very comfortable. I don’t know whether I answered your question or not, Donald.

Donald Lu – Goldman Sachs – Analyst

Yes. How about 2017, if –?

Morris Chang – Taiwan Semiconductor Manufacturing Company Ltd – Chairman

What? Well, 2017, the share is going to continue. We’re not going to lose the leadership on 16 market share once we recapture that in 2016. It’s going to continue 2017, 2018. And also both 20 and 16 are going to live longer than you might think now. Well 28, for that matter, will also live longer than you’d think.

Michael Chou – Deutsche Bank – Analyst

… Can we say your 16-nanometer market share in 2016 will be quite similar to your dominance in 28 nanometer, given that your 20 nanometer is the only provider? So the apple-to-apple comparison should be 28 to 16 nanometer.
Elizabeth Sun – Taiwan Semiconductor Manufacturing Company Ltd – Director of Corporate Communications
So market share in 16 nanometer in 2016, will that be the same as our market share at 28 nanometer, I would say, back in 2013, 2014?
Michael Chou – Deutsche Bank – Analyst Yes

Morris Chang – Taiwan Semiconductor Manufacturing Company Ltd – Chairman

Well, no, I don’t think so, because 28, of course we were virtually sole source. And 16, we already know we’re not. There’s at least one major competitor and then there’s another one that’s just eager to get in. I don’t mean that first competitor’s accessory, I mean another one.

Brett Simpson – Arete Research – Analyst

My question is around 28 nanometer. You’re running a large capacity at 28 nanometer at the moment. So can you share with us what your capacity plan is for 28? As you migrate more business to 20 nanometer and below over the next couple of years, do you intend to convert 28-nanometer capacity to lower nodes, or do you think you can keep the existing 28-nanometer capacity running full going forward.
Elizabeth Sun – Taiwan Semiconductor Manufacturing Company Ltd – Director of Corporate Communications
All right. Let me repeat Brett’s question so that people here can hear it better. Brett’s question is TSMC’s 28-nanometer capacity is very large. As our technology migrates to more advanced nodes, such as 20 and 16, in the next few years, what will be our plan on capacity of the 28 nanometer? Will we still have large demand to utilize those capacities or we need to do some changes?

Morris Chang – Taiwan Semiconductor Manufacturing Company Ltd – Chairman

Every — in every generation we worry a lot about the conversion loss we will suffer when we convert the equipment of that — the existing capacity of that generation to the capacity of the next generation. Now, so we do two things. First, we try to minimize that conversion loss. And since we’ve been living with the problem for so long now, I think we’re getting to be pretty good at it. So the conversion loss from one generation to another is normally in the low single digit, low middle single digit. Now the second thing we try to do is, and I think we actually have been doing it perhaps even more successfully than the first thing. The first thing was to try to minimize the conversion loss. The second thing we try to do is we try to prolong the life of each generation. And I was saying just five minutes ago that I think that the life of 28 nanometer may be longer than a lot of people think. And I mean it. Actually we’re still making half-micron stuff. And we try to prolong the life of every generation as we continue to migrate to advanced technologies. And 28 is certainly a generation that we want to prolong the life of.

Bill Lu – Morgan Stanley – Analyst

My first question is on 28 nanometers. If I look at your capacity this year versus 2014, how much is the increase in capacity?

Morris Chang – Taiwan Semiconductor Manufacturing Company Ltd – Chairman

High teens. High teens actually.

Gokul Hariharan – JPMorgan – Analyst

… First, I had a question on there’s been a lot of controversy about cost per transistor, whether Moore’s law — the economics of Moore’s law are slowing down. Your competitor Intel has put out a very emphatic statement saying that until 7 nanometer they’re seeing that continuing at the same pace as before. But there has been a lot of noise from the fabless community in the last couple of years that at 20 nanometer or at 16 nanometer there is a potential slowdown.

Could we have TSMC’s version now that you’re pretty much ready to start 10 nanometer and thinking already about 7? That’s my first question.
Elizabeth Sun – Taiwan Semiconductor Manufacturing Company Ltd – Director of Corporate Communications
So, all right. Let me repeat. Gokul, your question is mainly on the comments on cost per transistor. Some of the other players, I think you’re referring to Intel, who has made comments that they do see the cost per transistor to continue into 7 nanometer and so they can handle the economics of the Moore’s law. Whereas, on the other hand, fabless companies begin to complain about not seeing enough economics, starting with 20 nanometer. So what is TSMC’s statement regarding this economics issue?

Mark Liu – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO

Let me answer this question. The cost of transistor continues to go down. And by scaling mostly is — everybody knows, nobody I think has refused that statement — we see the cost of transistor continues going down in a constant rate. And in going forward, the cost of transistor going down probably at slightly slower rate. That’s the argument. But it really depends on companies. And for some companies simply do not have the technological capabilities. And today, further going down the Moore’s Law technology developments, just a few. And we — as far as whether those costs can — is — can get enough returns, and of course that has to do with how much that technology brings value to the product where they command the price. And today we see certain segments will continue to need that type of system performance to get enough return. So this is the reason we committed to push the system scaling.

Roland Shu – Citigroup – Analyst

Just a 10-nanometer question to C.C. Since, C.C., you said we are expecting to volume production of 10-nanometer in 2017. But I remember in the past two quarters actually our goal was to pulling in 10-nanometer mass production by end of 2016. So are we pushing out the 10-nanometer mass production schedule a little bit on that?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Ltd – President and Co-CEO

Let me explain that, because 10 nanometer, the mask layers is about 70 to 80. So you’ve got to start in 2016 to have output in 2017. So what I’m talking about is 2017 is to start to have revenue.

Q3 2014:

Lora Ho – TSMC – SVP & CFO

By technology, after two years of meticulous preparation we began volume shipments of 20-nanometer wafers. The revenue contribution went up from 0% to 9% of the third quarter wafer revenue. This is the fastest and the most successful ramp for a new technology in TSMC’s history.

Mark Liu – TSMC – Co-CEO


On 10-nanometer development, our 10-nanometer development is progressing according to plan. Currently we are working on early customer collaboration for product tape-outs in 4Q of 2015. The risk production date remain targeted at the end of 2015.

Our goal is to enable our customers’ production in 2016. To meet this goal, we are getting our 10-nanometer design ecosystem ready now. We have completed certification of over 35 EDA tools using ARM’s CPU core as the vehicle. In addition, we have started the IP validation process six months earlier than previous nodes with our IP partners.

We are working with over 10 customers on their 10-nanometer product design. The product plans show wide range of applications, including application processors, baseband, CPU, server, graphics, network processor, FPGA and game console. Our 10-nanometer will achieve industry-leading speed, power and gate density.

C.C. Wei – TSMC – Co-CEO


Next, I’ll talk about the 16-nanometer ramp and competitive status. In 16-nanometer, we have two versions, 16 FinFET and the 16 FinFET Plus.

FinFET Plus has better performance and has been adopted by most of our customers. 16 FinFET we began the risk production in November last year and since then have passed all the reliability qual early this year. For the FinFET Plus, we also passed the first stage of the qualification on October 7 and since then entered the risk production. The full qualification, including the technology and product qual, is expected to be completed next month.

So right now we have more than 1,000 engineers working on ramp up for the FinFET Plus. On the yield learning side, the progress is much better than our original plan. This is because the 16-nanometer uses similar process to 20 SOC, except for the transistor. And since 20 SOC has been in mass production with a good yield, our 16 FinFET can leverage the yield learning from 20 SOC and enjoy a good and smooth progress. So we are happy to say that 16-nanometer has achieved the best technology maturity at the same corresponding stage as compared to all TSMC’s previous nodes.

In addition to the process technologies, our 16 FinFET design ecosystem is ready also. It supports 43 EDA tools and greater than 700 process design kits with more than 100 IPs. All these are silicon validated. We believe this is the biggest ecosystem in the industry today.

On the performance side, compared with the 20 SOC, 16 FinFET is greater than 40% speed faster than the 20 SOC at the same total power or consumes less than 50% power at the same speed. So our data shows that in high-speed applications it can run up to 2.3 gigahertz. Or on the other hand, for low-power applications it consumes as low as 75 miniwatts per core.

This kind of a performance will give our customer a lot of flexibility to optimize their design for different market applications. So far we expect to have close to 60 tape-outs by the end of next year.

In summary, because of the excellent progress in yield learning and readiness in manufacturing maturity and also to meet customers’ demand, we plan to pull in 16-nanometer volume production through the end of Q2 next year or early Q3 year 2015. The yield performance and smooth progress of our 16 FinFET, FinFET Plus further validate our strategy of starting 20 SOC first, quickly follow with the 16 FinFET and FinFET Plus. We chose this sequence to maximize our market share in the 20-, 16-nanometer generation.

Next, I’ll talk about 28-nanometer status. We had strong growth in second quarter on 28-nanometer. And the business grew another quarter and accounted for 34% of TSMC’s wafer revenue in third quarter. On the technology side, we continue our effort to improve yield and tighten the process corners, so that our customer can take advantage of these activities and shrink their die size and therefore reduce the cost.

Let me give you an example. On 28LP, the polysilicon gate version, we now offer a variety of enhanced processes to achieve better performance. We also offer a very competitive cost so that our customers can address the mid- to low-end smartphone market. In addition to the 28LP, we also provide a cost-effective high-K metal gate version, the 28HPC for customers to further optimize the performance and the cost. Recently, we added another 28-nanometer offering we called 28 Ultra Low Power, for ultra low power applications obviously. We believe this 28ULP will help TSMC customers to expand their business into the IoT area.

In summary, we expect our technology span in 28-nanometer node will enhance TSMC’s competitiveness and ensure a good market share. We also expect the strength of the demand for our 28-nanometer will continue for multi years to come. In response, we are preparing sufficient capacities to meet our customers’ future demand.

Q2 2014:


Morris Chang – TSMC – Chairman

Now a few words on 20-nanometer and 16-nanometer progress. In the last two and half to three years, 28-nanometer technology has driven our growth. In the next three years, 20 and 16-nanometer technologies are going to drive our growth; 28 in the last two and half to three, 20 and 16 in the next three.

After two years of meticulous preparation, we began volume shipments of our 20-nanometer wafers in June. The steepness of our 20-nanometer ramp sets a record. We expect 20-nanometer to generate about 10% of our wafer revenue in the third quarter and more than 20% of our wafer revenue in the fourth quarter. And we expect the demand for 20-nanometer will remain strong and will continue to contribute more than 20% of our wafer revenue in 2015. It will reach 20% of our total wafer revenue in the fourth quarter of this year and it will be above 20% of our total wafer revenue next year.

The 16-nanometer development leverages off 20-SoC learning and is moving forward smoothly. Our 16-nanometer is more than competitive, combining performance, density and yields considerations. 16-nanometer applications cover a wide range including baseband, application processors, consumer SoCs, GPU, network processors, hard disk drive, FPGA, servers and CPUs. Volume production of 16-nanometer is expected to begin in late 2015 and there will be a fast ramp up in 2016. The ecosystem for 16-nanometer designs is current and ready.

A few years ago, in order to take advantage of special market opportunities, we chose to develop 20-SoC first and then quickly follow with 16-nanometer. We chose this sequence to maximize our market share in the 20/16-nanometer generation. As the 20/16 foundry competition unfolds, we believe our decision to have been correct.

Number one, in 20-SoC, we believe we will enjoy overwhelmingly large share in 2014, 2015 and onwards.

Number two, in 16-nanometer, TSMC will have a smaller market share than a major competitor in 2015. But we’ll regain leading share in 2016, 2017 and onwards.

Number three, if you look at the combined 20 and 16 technologies, TSMC will have an overwhelming leading share every year from 2014 on.

Number four, in total foundry market share, after having jumped 4 percentage points in 2013, TSMC will again gain several percentage points in 2014. This is the total foundry market share covering all technologies. After having increased 4 percentage points last year, TSMC will gain another several percentage points this year.

Now a few words about 10-nanometer. The 10-nanometer development is progressing well. The 10-nanometer speed is 25% faster than the 16-nanometer. The power consumption is 45% less than 16-nanometer and the gate density is 2.2x that of the 16-nanometer. Power is 25% faster. Did I say power? I meant speed. Speed is 25% faster, power is 45% less, gate density 2.2 times more, all compared with 16-nanometer.

We work closely with our key customers to co-optimize our 10-nanometer process and design. We expect to have customer tape outs in the second half of 2015.

William Dong – UBS – Analyst

Good afternoon Mr. Chairman. I guess — we keep talking about technology. I guess the question I want to ask is that with all this rush to continue to push down technology roadmap, to go down to 16, to 14 and to 10 nanometer, what are our thoughts about what’s driving this demand? As we move toward, for example, Internet of Things, is there such a requirement to keep pushing on the technology front to actually have enough, sufficient demand to keep driving it down?

Morris Chang – TSMC – Chairman

Well, if the cost is low enough — cost is very much a part of the equation. If the cost is low enough, the demand will increase because we can see a lot of applications that are just waiting there. Of course I’m talking about the mobile products, but I’m also talking about Internet of Things, so wearables and so on, so on, Internet of Things. The applications are just waiting there for better, for faster speed and lower power and higher density ICs. Cost is definitely in the equation.

So, yes, when you ask will the demand be there. If we can get the cost down to an acceptable level, demand will be there. And of course that’s why — that’s how things like EUV come into the question. Nobody has asked about that yet. We actually were prepared to answer that with the same answer that we gave you last time, by the way, that we are still planning to — there’s still a possibility to use EUV on one, one or two — or just one layer in the 10 nanometer, yes. One layer, one layer in 10 nanometer and 7 I think is, of course, an even better candidate.

Dan Heyler – BofA-Merrill Lynch – Analyst

Hopefully this question simplifies and doesn’t complicate things. Just to make sure I understand this share loss thing, so basically what you’re saying is the share loss at 16, these are customers that are choosing to skip 20? Is that how should I think of this that these are not any — are any of these customers that are currently 20 that are going to 16 next year or is this all people that are choosing to skip 20?

Morris Chang – TSMC – Chairman

Well, first of all, I want to question the word share loss. I don’t consider there is share loss because just like 32/28 we had zero share in 32. But then we were very successful in 28. The two really belong to the same generation. And 20 and 16 also belong to the same generation. So, yes — and share loss means that you start with something and then you lose it, it becomes less. Well, this year nobody has — everybody has zero share, okay. And I am just saying that we will start on 16, we will start with a lower share than we did with 20 or 28. We start with a lower share than we did with 20 or 28. And then we’ll get back to a high share in 2016. I’m just arguing with him, but he did have a question; what was that?

Dan Heyler – BofA-Merrill Lynch – Analyst

Or just simply are your — are these customers moving to 16, are these the ones that have currently been on 20 or are these the guys that have skipped because the debate in the industry is should we go straight to 16 and skip 20. So are these customers that have basically been at 28 and are skipping 20 and going straight to 14 at your competitor?

Morris Chang – TSMC – Chairman

Mainly because our customers wanted it sooner. We got in a little late, as I said; our customers wanted it sooner. So that’s why we’re starting — and we’ll catch up only a little later.

Michael Chou – Deutsche Bank – Analyst

Chairman, regarding the 16/20 nanometer, could we say your total market share in 16 and 20 nanometer will be similar to 28/32 for the corresponding period? Can we say that?


Morris Chang – TSMC – Chairman

The combined 20 — I just ran an analysis just a couple of weeks ago, so I know exactly the answer to your question. The combined 20/16 market share in the first two years of its existence, which is this year and next year — well, I guess I have to add in 2016 — the combined — our combined 20/16 share in 2014, 2015 and 2016 will still be greater than our combined share of 32 and 28 in 2012, 2013 and 2014.

Q1 2014:


Mark Liu – Taiwan Semiconductor Manufacturing Company Ltd – President & Co-CEO

Then I cover the updates on 16 FinFET, 16 FinFET plus and our 10 FinFET. First, we have two general offers for customers, 16 FinFET and 16 FinFET plus. 16 FinFET plus offers 15% speed improvement, the same total power, compared to 16 FinFET. More importantly, 16 FinFET plus offers 30% total power reduction at the same speed, compared to 16 FinFET.

Our 16 FinFET plusmatches the highest performance among all available 16-nanometer and 14-nanometer technologies in the market today. Compared to our own 20 SoC, 16 FinFET plus offers 40% speed improvement. The design rules of 16 FinFET and 16 FinFET plus are the same; IPs are compatible.

We will receive our first customer product tapeout this month. About 15 products planned for 2014, another about 45 in 2015. Volume production is planned in 2015. Since 95% tools of 16 and 20 are common, we will ramp them in the same gigafabs in TSMC. 16 FinFET yield learning curve is very steep today and has already caught up with 20 SoC. This is a unique advantage in TSMC 16-nanometer.

For 10 FinFET, 10 FinFET offer TSMC’s third generation FinFET transistor, designed to meet the power and the performance requirement of mobile computing devices. 10 FinFET will offer greater than 25% speed improvement, the same total power, compared to 16 FinFET plus. More importantly, 10 FinFET offer greater than 45% total power reduction at the same speed, compared to 16 FinFET plus.

10 FinFET will offer 2.2X of density improvement over its previous generation, 16 FinFET plus. So, currently, 10 FinFET development progress is well on track, but risk production will be in 4Q 2015. Above are the key messages on three items.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Ltd – President & Co-CEO

…  I would like to take this opportunity to share with you the two topics with you; namely, the 20 SoC ramp and TSMC’s advance assembly solution to our customer. First, I will brief you on the status of 20 SoC ramp.

Let me recap what we had said in the last meeting here. We started 20 SoC production in January this year and by fourth quarter of this year, the 20 SoC will account for 20% of the quarterly revenue — wafer revenue. And for the whole year of 2014 we expect 20 SoC will be about 10% of our total wafer revenue of the year of 2014, of course. All these expectations remain the same today.

Now, there are some major achievement I would like to share with you. First, on the ramping speed. 20 SoC by far is the fastest ramping in TSMC’s history. Of course, this fast ramp is to meet customers’ strong demand. And I believe this production of 20 SoC in TSMC represents one of the largest mobilization in semiconductor history. Let me share with some numbers, so you can have a snapshot on this ramp.

In about one year’s time we have built a manufacturing team of 4,600 engineers and 2,000 operators in two fabs; Fab 14 in Tainan and Fab 12 in Hsinchu. More impressively, in the same time period, close to one thousand engineer has been relocated among TSMC’s fabs in Hsinchu, Taichung and Tainan. All these are prepared for the 20 SoC’s ramp-up. This magnitude of mobilization, I believe, is not an easy job. We move people around that show our strength in manufacturing and this highly mobilization is not moving the tool or just a handful around. We’re talking about we’re moving the engineer and operator among TSMC’s fabs. In the meanwhile, we have installed more than 1,500 major tools for this 20 SoC ramp.

Of course, the faster ramp has done with a very good device reliability and a very good wafer defect density. Without those, the fast ramp will make no sense. Now how important are these 20 SoC ramp? Well we knew that 28 nanometer provided the engine of TSMC’s profitable growth in the years of 2012 and 2013 and similarly, we expect 20 SoC will provide the engine of TSMC’s profitable growth in year 2014 and 2015.

Now let me switch gear to advanced assembly technologies. The purpose of — for us to develop advanced assembly technology is to provide our customer a better performance and a lower power consumption, while at a lower cost as compared to the previous assembly solution. For example, we have developed CoWoS and CoWoS has been developed to connect two dies or more dies together to have a very high performance and a very low power consumption and today CoWoS is in a small volume production already. However, the cost structure of CoWoS has made CoWoS only suitable for some very high performance applications and the products. To address the cost structure issue and for those mobile — very large volume mobile devices, we have developed a derivative technology called InFO; that stands for integrated fan-out.

InFO will have significant lower cost as compared to CoWoS and at the same time, InFO also can have the same capability to connect multiple dies together just as the CoWoS did. Currently, we’re working with major customers and the InFO, to incorporate this structure into their future product. We have delivered many functional dies to our customers already and the process optimization are ongoing.

In fact, we are very excited about TSMC’s advanced assembly technology development as we’re building a innovative solution for our customers product, which requires high performance, lower power consumption and at a very reasonable cost structure.

Michael Chou – Deutsche Bank – Analyst

I don’t know, C.C. Wei, could you give us more color on the advanced packaging you just mentioned. What’s the difference between this one and CoWoS?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Ltd – President & Co-CEO

The difference between the InFO and the CoWoS is actually the geometry to connect multi-dies together. In the CoWoS, actually we are using very small geometry, actually 65 nanometers of geometry to connect the multi-dies together. In InFO, we’re using the larger geometry, which are still technical confidential information. But the cost is much, much lower.

Brett Samson – Arete Research – Analyst

Just had a quick question. Can you give us a sense within the 28 nanometer nodes, how does that split between poly-SiON and high-K and how do you think this might trend through this year?
Elizabeth Sun – Taiwan Semiconductor Manufacturing Company Ltd – Director, Corporate Communications
So Brett’s question is what is really the mix between poly-SiON, that is our 28 LP, versus our high-k metal gate and what is going to be the trend with respect to that kind of mix throughout this year?

Mark Liu – Taiwan Semiconductor Manufacturing Company Ltd – President & Co-CEO

Allow me to answer that. Our 28 nanometer high-k metal gate has three options, 28HP, 28HPM and 28HPC. And this year these 28 high-k metal gate technology will be about 85% of the overall 28 nanometer in terms of the wafer.

Dan Heyler – Bank of America Merrill Lynch – Analyst

… I want to follow up on this InFO, this is quite interesting. Could you just maybe elaborate a bit more on what exactly are you going to be attaching, so which devices are we talking about in terms of what – with CoWoS it was pretty much PLD [Programmable Logic Devices, like Altera] companies were there and others, some baseband. So what devices are you attaching on the initial generation between the different chips? And second part of that question would be what kind of — how many customers do you expect to manage to have in this area, because you start peddling lots of devices and lots of customers it gets really complicated, you start to look more like an OSAT [Outsourced Semiconductor Assembly and Test]. So I wonder if this is going to be a pretty small group of high volume products? And finally on — as you attach — are you actually doing a chip attach or will you be doing only the wafer level activity and will you be having — working with the OSATs to do the actual chip attach?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Ltd – President & Co-CEO

Dan, to answer your question, the InFO actually we’re right now working on application processor together with memory dies. That’s good enough for you. I cannot say anything more than that. We’re working with mobile product customers and we did not — we expect very high volume, but we did not with many, many customers as current status. We’re working on the wafer level process, stacking die, and couple of them, we’re able to do the complete line all here.

Q4 2013:


Morris Chang – Taiwan Semiconductor Manufacturing Co., Ltd. – Chairman

Good afternoon, ladies and gentlemen. Today, our comments are scheduled as on the slide on your left. First, I’m very glad to have the opportunity to introduce our new top management team.

I’d first start with Lora, although I think everyone knows Lora well. Lora has a bachelor’s degree from Chengchi University, a master’s degree from National Taiwan University, both degrees in finance. She worked for Cyanamid, Wyse, Thomas & Betts and TI-Acer before she joined TSMC in 1999. And she has been TSMC’s CFO since 2003.

Next, Dr. C. C. Wei. C. C. has a bachelor’s degree from Chiao Tung University and a Ph. D. from Yale University, both in electrical engineering. C. C. worked for TI, SGS, Chartered before joining TSMC in 1998. C. C. has been Senior VP of Operations, Senior VP of Business Development, Co-COO, and in the Co-COO job CC was successively responsible for R&D and Operations. Now C.C. is President and Co-CEO.

C.C. is 60 years old and I should add that Lora is 57 years old.

Mark Liu; Mark has a B.S. from National Taiwan University and a Ph. D. from Berkeley, both in electrical engineering and computer science. Mark worked for Intel, Bell Telephone Labs before joining TSMC in 1993. And at TSMC he has been VP, Senior VP of Operations and he was also a Co-COO, and all the time he was Co-COO he was responsible for our sales, marketing and planning.

And now Mark and C.C. are Presidents and Co-CEOs of the Company. Mark is 59 years old.

C.C. Wei – Taiwan Semiconductor Manufacturing Co., Ltd. – President & Co-CEO
[about the technology aspects of TSMC’s growth engine]

Good afternoon everybody. I am C.C. Wei and I will give you the update of our 28-nanometer high-K metal gate version. Let me recap the history. We started 28-nanometers volume production in year 2011 mainly on the 28LP, the oxynitride version. And since then the business continued to grow. So last year, we had tripled 28-nanometers of business versus year 2012. That in this year, year 2014, the business for 28-nanometer will continue to grow at least by another 20%, and all the increase are coming from the 28-nanometers high-K metal gate version, which is we name it 28HPM.

Let me add more color to it. We expect we’re going to have about more than 100 tape-outs from about 60 customers in this year in 28HPM. Now you may ask it why? Why there are so many products that were designed on this technology? One of the main reason I can give it to you is the performance, the superior performance. For example, 28 HPM compare with the 28LP that will gain another 30% of the speed at the same kind of power consumption, or you can say that at the same power consumption — at the same speed, you will consume 15% less power. And everybody knows that the power consumption in the mobile device is very important. That’s why we think we have a very high, good business on the 28 HPM.

Now, furthermore, after the 28HPM, we also offer 28HPC, which is a low-cost version of the 28HPM. The 28HPC is developed to meet the customers’ demand to compete in the mid-to-low-end smartphone market. We expect that this 28HPC will have a very strong demand in the next two years. That’s what we have.

Okay, let me give you some information on the competition to explain why we are so confident on this 28 nanometers high-K metal gate business. If you still remember that long time ago, we mentioned about gate-first and gate-last. Still remember that terminology? All right. So, simply to say that gate-last version will give you better performance and a better process control. As a result, all our customers will enjoy using the gate-last versions that technology to have a higher or better performance than other products which are designed with a different approach.

In addition to that I’ll say that because of the better process control and TSMC’s manufacturing excellence, we have a much better yield than our competitor, so that our customer will enjoy the lower die cost. That’s what we have. And that’s why we explained that our confidence that the 28 nanometers business continue a very good business for us.

Now, let me switch the gear to 20-SoC. That’s another exciting news that we have, I want to share with you. 20-SoC is a technology that we developed to enable TSMC’s customer to lead in the mobile device market. And this technology we are believe in this year, next year, well I have a very good business to capture. So, what is the status now of the 20-SoC? We have two fab, Fab 12 and Fab 14 that complete the qual of 20-SoC. And as a matter of fact, we started production. We are in volume production as we speak right now. So, it’s in the high-volume production as we are speaking right now.

Let me add more information to that. First, there are more than $10 billion had been committed to build capacity. Second, we have more than 2,500 engineers and 1,500 operators right now in manufacturing, doing the 20SoC volume production. The ramping rate will be the fastest one in TSMC’s history. Using the ramping rate, you can get the hint of the business, how big the business is.

Another fact to share with you, we have probably — at the end of this year, we have more than dozens of tape-out from about a dozen customers that they are producing the 20SoC product, okay? You may ask, good business, how about the competition? If you have a very strong competition, you might — cannot have too much of confidence on the future. Let me talk about the competition.

I’m very confident that our 20SoC is the highest gate density in volume production at 20 nanometers node. And please remember that; highest gate density and a high volume production. I don’t see any company today can claim on this kind of production and with this kind of gate density at this time, nobody. And most of our competitors, to be frank with you, they’re not even into this game yet. So we are confident to have a good business that will contribute to TSMC’s revenue — wafer revenue by probably around 10% this year. And with that I conclude my presentation and thank you for your attendance.

Mark Liu – Taiwan Semiconductor Manufacturing Co., Ltd. – President & Co-CEO
[about TSMC’s competitiveness versus Intel and Samsung]

I will start this topic by update you our recent development status of our 16-FinFET technology. 16-FinFET technology has been a very fast paced development work in TSMC and we have achieved the risk production milestone of 16-FinFET in November 2013, November last year. And this month, we should pass the 1,000 hours so-called the technology qualification. So the technology is ready for customer product tape-out.

Our 16-FinFET yield improvement has been ahead of our plan. This is because we have been leveraging the yield learning of 20SoC. Currently 16-FinFET SRAM yield is already close to 20SoC. And with this status we are developing an enhanced transistor version of 16-FinFET plus, with 15% performance improvement. It will be the highest performance technology among all available 16 and 14 nanometer technology in 2014. The above progress status is well ahead of Samsung.

Let me comment on the Intel’s recent graph shown in their investor meetings, showing on the screen. We usually do not comment on other company’s’ technology, but this is — because this has been talking about TSMC technology and as Chairman said, has been misleading. To me it’s erroneous, based on outdated data. So I like to make the following rebuttal.

futureICT - 2013--Intel Is Committed to Press Ahead on Density - Enables a 'Transistor Like' Lead in Density

2013: Intel Is Committed to Press Ahead on Density – Enables a “Transistor Like” Lead in Density

futureICT - Jan-2014--Density Comparison by TSMC vs Intel 2013 statement

January 14, 2014: Density Comparison by TSMC vs. Intel’s 2013 statement at its Investor Meeting

On this view graph, the vertical axis is the chip area on a log scale. Basically this is compared at chip area reduction. On the horizontal axis, it shows four different technologies; 32/28, 22/20, 14/16-FinFET and 10-nanometer. 32 is Intel technology and 28 is TSMC technology. So is the following three nodes; the smaller number 20, but on 14-FinFET is Intel, 16-FinFET is the TSMC. On the view graph shown at Intel investor meeting, it is with the grey plots showing here. The grey plots shows the 32 and 20 nanometer, TSMC is ahead of the area scaling, but however, with 16, the data, grey data shows a little bit uptick. And following the same slope, go down to the 10 nanometer. What’s the correct data we show on the red line, that’s our current TSMC data. The 16, we have been volume production on 20 nanometer, as C.C. just mentioned, this is the highest density technology in production today.

We took the approach of significantly using the FinFET transistor to improve the transistor performance on top of the similar back-end technology of our 20 nanometer. Therefore, we leveraged the volume experience into volume production this year, to be able to immediately go down to 16 volume production next year, within one year. And this transistor performance and innovative layout methodology can improve the chip size by about 15%. This is because the driving of the transistor is much stronger, so that you don’t need such a big area to deliver the same driving circuitries.

And for the 10 nanometer, we haven’t announced it, but we did communicate with many of our customers that that will be the aggressive scaling of technology we’re doing. And so, in the summary, our 10 FinFET technology will be qualified by the end of 2015. 10 FinFET transistor will be our third generation FinFET transistor. This technology will come with industry’s leading performance and density. So, I want to leave this slide by 16 FinFET scaling is much better than Intel said, but still a little bit behind Intel.

However, the real competition is between our customer’s product and Intel’s product or Samsung’s product. TSMC’s Grand Alliance; that is the alliance of us, our customers, EDA, IP, communities and our supplier is the largest and the only open technology platform for the widest range of product innovations in the industry today. As for the tape-out of our 16 FinFET, more than 20 customer product tape-outs on 16 FinFET technology is scheduled this year already. They include wide range of applications; baseband, application processors, application processor SoCs, graphics, networking, hard disk drive, field programmable array, CPUs and servers. Our 16 FinFET technology captured the vast portion of products in the semiconductor industry.

We’ve been actively working with our customer’s designer on this since last year. TSMC’s speed and productization of the customer’s product and our ability to execute for a short time-to-market for a customer are far superior than Intel and Samsung.

Lastly, I would comment on the mobile products. With this 16 FinFET technology and the innovations of processor architecture and various IP from our customers, we are confident that this planned, 16 FinFET mobile product, which is going to tape out to us, will be better than Samsung’s 14 nanometer and better than Intel’s 14 SoC. Thank you very much.

Roland Shu – Citigroup Global Markets – Analyst

… Is the 16-plus is improving from the design you were saying or this is just for the performance enhancement or are we going to consider to change our 16-plus to — even to the — same as the 14-nanometer? …

Mark Liu – Taiwan Semiconductor Manufacturing Co., Ltd. – President & Co-CEO

16 FinFET-plus is a transistor enhancement. For the design — back-end design rule are similar to 16 FinFET, therefore designer can design on 16 FinFET and re-characterize, upgrade their product performance. This transistor, as I mentioned, also can reduce the cell size, standard cell size, and with the enhanced performance transistor. That’s the way to reduce the chip size. So we do not intend to change the naming. I mean this is engineering, this is the word — this is the name that we chose earlier based on the physical consistent number and we do not intend to change name.

Randy Abrams – Credit Suisse – Analyst

My first question on the management structure now with the Co-COOs promoted to Co-CEOs. If you could talk about how the responsibilities would change with their promotion to Co-CEO? And for yourself, Dr. Chairman, how will your activities change versus before this move? So if you could talk about the roles for each of the different Co-CEOs and yourself now.

Morris Chang – Taiwan Semiconductor Manufacturing Co., Ltd. – Chairman

We started with President and the Co-CEO in November, and it has been now two months. And if you ask me now, has my life changed in the last two months? My answer is no. It has not changed. But I think that my effort, my time has been spent more on the coaching aspects. I think that — I do believe that I do more coaching. If I spend 100 hours and — I now perhaps spend 20 hours of the 100 hours on coaching, whereas in the past, I’d probably spend only 5 or 10 hours of the 100 hours on coaching.

Now, actually, this is an overseas call, is this correct? Yes. So let me just explain very briefly what the Taiwan law and customs are in relation to a Chairman’s authority and responsibility. Basically, by both law and custom, the Chairman of a company has the ultimate authority and responsibility, basically. However, he may delegate his authority and responsibility to the President. He may also take it back anytime. He can delegate any and all, any or all of the responsibilities to the President. And now these two gentlemen, their titles is President and co-CEO. President comes first. They are, in a very legal sense, Presidents. Now the co-CEO is basically a Western term. And then in the United States, a CEO usually bears the final ultimate responsibility and authority as a Chairman in Taiwan does. In the US, it’s the CEO. Now — so my role in the future is really to convert these two gentlemen from the Taiwan sense President to the US sense CEO, and it will be a gradual process.

Donald Lu – Goldman Sachs – Analyst So Chairman, (spoken in foreign language).

First question is, I want to ask the Chairman, how would you — are you satisfied with the transition so far and also, how the two Presidents would share their work? Are they still rotating or not? And (multiple speakers) but probably not now. And maybe give us some details about how the Company is run. And I have a follow-up question on competition.

Morris Chang – Taiwan Semiconductor Manufacturing Co., Ltd. – Chairman

All right. I am quite satisfied with the transition. And these two gentlemen; Mark is now responsible for sales, marketing, strategic planning, business development, and yes, information technology and materials management, all those. And C.C. is responsible for operations, all the operations, and he is also responsible for specialty technology R&D. Specialty technology incidentally accounts for 25% of our total business. So now, Donald, your other question is whether they’re going to rotate. My plan currently is, I don’t plan it that way, I don’t plan it that way right now. However, I deem it’s a pretty flexible thing. Tomorrow, I may take one part of Mark’s and give it to C.C. or vice versa. But I’m not considering rotation, per se. Yes, does that answer your first question?

Donald Lu – Goldman Sachs – Analyst

… Okay, since we are already doing it, why don’t you give us more color? 16-nanometer, for example, are we saying that in terms of die size, performance, our product will be very similar to Intel’s 40-nanometer FinFET? And also, Mark commented that for the FinFET tape-outs, specifically there’s a CPU and server chips, and can we say that TSMC’s CPU and server chips will have the similar physical performance as Intel’s products today?

Morris Chang – Taiwan Semiconductor Manufacturing Co., Ltd. – Chairman

Well, I think, Donald, we have already given everybody enough information on our 16-FinFET. I think that if we keep giving more, we would be helping our competitors who have picked on us. And so, now, we do stand on what we said. We are going to — our Grand Alliance will out-compete Intel and Samsung. Our Grand Alliance on the 16-FinFET will out-compete. By that I don’t mean that we’ll completely exclude them, no, no, no. We can’t do it. We won’t be able to do that. But our Grand Alliance, with us as foundry supplier, will capture a large share of the 16-nanometer. You agree with that don’t you?

Mark Liu – Taiwan Semiconductor Manufacturing Co., Ltd. – President & Co-CEO

The fabless companies in China are very aggressive approaching leading-edge technologies. To tell you, our 16-FinFET this year, already some of the fabless companies will be using it in tape-outs. So, I think all those fabless companies’ subsidy will propel them into the leading-edge technology more.

July 20, 2013: TSMC takes on rivals with Grand Alliance strategy, says Chang [Global Data Point] by TMC News

(Global Data Point Via Acquire Media NewsEdge) Taiwan Semiconductor Manufacturing Company (TSMC) chairman and CEO Morris Chang, at a July 18 investors conference, talked about the importance of the foundry’s close ties with customers and ecosystem partners, and described how TSMC has formed a “Grand Alliance” with EDA, IP, software IP, systems software and design services providers.

TSMC has been competitive against fellow pure-play foundries, said Chang. In the face of rising competition from IDMs, TSMC with its ability to deliver cutting-edge technologies and advanced manufacturing capacity is also able to outshine the rivals, Chang indicated.

With the industry moving towards sub-20nm technologies, Chang believes that TSMC will become more capable of fending off rivals like Samsung Electronics and Intel. “Now in this new era of competition, the competition is not between foundries. It is not between foundries and IDMs. It is between ‘Grand Alliances’ and IDMs,” Chang pointed out.

Chang named ARM, Imagination, Cadence and Mentor as some of TSMC’s IP and EDA partners.

TSMC’s so-called “Grand Alliance” seems like an expansion of its Open Innovation Platform (OIP), which was announced in 2008. TSMC’s OIP is a business strategy aiming to provide integrated services from design to manufacturing to testing and packaging. According to TSMC, the platform is to bring together the thinking of customers and partners under the common goal of shortening design time, minimizing time-to-volume and speeding time-to-market.

In addition, Chang noted that TSMC’s 28nm process technology is on track to triple in wafer sales in 2013. TSMC made 29% of its NT$155.89 billion (US$5.18 billion) revenues from selling 28nm chips in the second quarter of 2013.

Chang also reiterated TSMC’s plans that 20nm technology will begin volume production in early 2014, followed by volume production of 16nm FinFETs within one year.

About Nacsa Sándor

Lazure Kft. • infokommunikációs felhő szakértés • high-tech marketing • elérhetőség: snacsa@live.com Okleveles villamos és automatizálási mérnök (1971) Munkahelyek: Microsoft, EMC, Compaq és Digital veterán. Korábban magyar cégek (GDS Szoftver, Computrend, SzáMOK, OLAJTERV). Jelenleg Lazure Kft. Amire szakmailag büszke vagyok (időrendben visszafelé): – Microsoft .NET 1.0 … .NET 3.5 és Visual Studio Team System bevezetések Magyarországon (2000 — 2008) – Digital Alpha technológia vezető adatközponti és vállalati szerver platformmá tétele (másokkal együttes csapat tagjaként) Magyarországon (1993 — 1998) – Koncepcionális modellezés (ma használatos elnevezéssel: domain-driven design) az objektum-orientált programozással kombinált módon (1985 — 1993) – Poszt-graduális képzés a miniszámítógépes szoftverfejlesztés, konkurrens (párhuzamos) programozás és más témákban (1973 — 1984) Az utóbbi időben általam művelt területek: ld. lazure2.wordpress.com (Experiencing the Cloud) – Predictive strategies based on the cyclical nature of the ICT development (also based on my previous findings during the period of 1978 — 1990) – User Experience Design for the Cloud – Marketing Communications based on the Cloud
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One Response to The Dawn of the SoC 2.0 Era: The TSMC Perspective

  1. Pingback: ARM CPU roadmap revealed: Ares, Prometheus, Ananke and Mercury in development | KitGuru

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