Home » Cloud Computing strategy » Applying 2-16 cores of ARM Cortex-A15 in ‘2014 vintage’ LSI Axxia SoCs that will power next-generation LTE basestations from macrocells to small cells opening upto 1000 times faster access to the cloud by 2020

Applying 2-16 cores of ARM Cortex-A15 in ‘2014 vintage’ LSI Axxia SoCs that will power next-generation LTE basestations from macrocells to small cells opening upto 1000 times faster access to the cloud by 2020

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OR LSI Corporation’s ARM Cortex-A15 based 2-16 core SoCs with similar number of LSI’s specialized networking accelerators inside to drive the next-generation LTE base stations (from femto- through pico- and micro- to macro- and metrocells) boosting the cloud clients to get out of the current infancy of the mobile Internet OR Cooperation of LSI Corporation with ARM on highly scalable and energy efficient multicores and cache coherent interconnect for them within an SoC now enhanced with a joint LSI and Nokia-Siemens Network effort to improve real-time performance, I/O optimization, robustness and heterogeneous operating environments on multi-core SoCs, also carried out within the newly setup Linaro* Networking Group OR How ARM’s Cortex-A15 to A57 (32-bit to 64-bit) micro-architecture roadmap is going to be enhanced by an upto 16 core SoC architecture developed by LSI Corporation now and with more than 16 cores in the future (with Cortex-A57) which will enable Nokia-Siemens Networks to fullfill its vision of “1 GB per day revolution by 2020” for which a 1000x increase** in traffic throughput will be needed

* From p. 38 of ARM Annual Report 2012 [March 1, 2013] “In 2010 ARM helped launch Linaro, an open source software not-for-profit organisation which [among others] enriches the software toolkit for Android phones. By summer 2012 the results looked pretty impressive, with a reported 100% performance improvement for the Android 4 operating system. See Linaro Android is up to twice as fast as stock Android [AndroidAuthority.com, June 5, 2012]”
** Note that Qualcomm is also working along this vision as evidenced by its Products & Services: Wireless Networks Technology 1000x Data Challenge Overview [Aug 22, 2012], Spectrum [Sept 24, 2012], Small Cells [Oct 1, 2012] and Efficiency [Oct 1, 2012] pages of declaring its corporate intents. This was also one of the focus demos and presentations from Qualcomm on the MWC 2013 last week as evidenced by their The 1000x Mobile Data Challenge at Mobile World Congress [QUALCOMMVlog YouTube channel, Feb 22, 2013] video serving also as a good background intro here
With Generation M on the rise, mobile data usage continues to climb. If we don’t step up to the 1000x challenge we will see lower speed, slower downloads and more congestion. We aren’t in the business of forecasting when 1000x will happen but we are focused on finding a solution that makes 1000x possible.

First watch the LSI Axxia video report from MWC 2013:     Axxia Processor Familyimage

LSI Axxia 5500 announced, 16-core ARM Cortex-A15 for network infrastructure [Charbax YouTube channel, Feb 28, 2013]

Troy Bailey: [5:40] Will be sampling in early third quarter … Mass production typically is a six to nine months process after that (i.e. 2014) to validate and also to work with customers to get their products ready to go out. [5:54]

LSI designs semiconductors and software that accelerate storage and networking in datacenters and mobile networks. At Mobile World Congress 2013, LSI is introducing the Axxia 5500 16-core ARM Cortex-A15 to provide scalability, performance and low power consumption to meet the growing demand for mobile broadband.

Next watch 4G World 2012: The 1-Gigabyte Revolution [LightReadingTV YouTube, Nov 2, 2012] (on the same Oct 29 – Nov 1 conference)

Bill Payne, Head of Advanced Technologies, CTO North America at Nokia Siemens Networks, speaks at 4G World in Chicago about “engagement economy” leading to the “1 GB per day revolution by 2020” for which there is the need to provide a 1000x increase in traffic throughput


For which it was announced at MWC 2013 that Nokia Siemens Networks and LSI Collaborate on Wireless Infrastructure Solutions [LSI press release, Feb 21, 2013]

LSI® Axxia® platform and SoC capabilities contribute to
higher-performance mobile broadband solutions
Nokia Siemens Networks and LSI Corporation (NASDAQ: LSI) announced today a collaborative framework with ARM® processor based System-on-Chips (SoCs) that enable enhanced support for real-time performance, I/O optimization, robustness and heterogeneous operating environments on multi-core SoCs.
Nokia Siemens Networks is increasing investment in technology development in mobile broadband business and actively participating in Linaro Networking Group and to ARM ecosystem in general to enable better use of Open Source Linux®software and tools. This will both enhance performance of forthcoming base station BTS products as well as drive towards lower power consumption.
“LSI is very pleased to be collaborating with Nokia Siemens Networks on innovative mobile broadband solutions,” said Jim Anderson, general manager for LSI’s Networking Solutions Group. “The LSI Axxia line combines ARM processor cores with our unique Virtual Pipeline™ acceleration technology to create a platform for next-generation mobile broadband solutions and other applications. Our advanced software and emulation capabilities ensure accelerated time to market for our customers.”

Complement this with the following two videos produced by Qualcomm for MWC 2013:
Neighborhood Small Cells [QUALCOMMVlog YouTube channel, Feb 22, 2013]

An innovative deployment model to enable extremely low-cost, plug-and-play, open, unplanned small cells networks. Qualcomm’s UltraSON suite of interference and mobility management techniques makes such models a reality by solving interference challenges and by offering seamless mobility. Neighborhood small cells is a key enabler to meet the 1000x data challenge

LTE Advanced Opportunistic Small Cells [QUALCOMMVlog YouTube channel, Feb 22, 2013]

Captures the 2013 MWC demonstration of small-cells that dynamically turn on/off based on proximate users, a feature important for the very dense small cell deployments as envisioned to meet the 1000x data challenge. The demo utilizes Qualcomm’s live over-the-air LTE Advanced small-cell network in San Diego. It also incorporates relay nodes and shows the coexistence of HetNets range expansion (eICIC-IC) and VoLTE service.


LSI Axxia background:

Axxia Communication Processor AXM5500 [LSI promotion site, Feb 19, 2013]

Accelerating Next Generation Networks Mobile Networks

  • Enabling one architecture for heterogenous networks
  • Leveraging software and hardware investments
  • Accelerating time-to-revenue
First 16 core ARM based Multicore Processor for Mobile Networks
The Axxia® Communication Processor AXM5500 product family is designed to accelerate performance and increase power efficiency for mobile networks. The Axxia 5500 series combines 16 ARM cores with LSI’s specialized networking accelerators to offer networking service providers more capable and intelligent wireless infrastructure equipment, including multi-radio base stations, mobile backhaul equipment and gateways.
Leading Technology
The AXM5500 is the industry’s first multicore communication processor to be available with ARM’s new CoreLink™ CCN-504 interconnect technology, which provides the end-to-end quality of service needed for networking applications.
Power Efficiency
LSI’s latest semiconductor manufacturing technology combined with ARM’s power efficient cores more than double the amount of data that can be processed by the Axxia 5500 at the same power level.
Extensive Scalability
The Axxia 5500 platform architecture can scale to meet the performance required for 4G LTE and other data intensive networking applications.
Networking Expertise
LSI’s unique Virtual Pipeline technology efficiently accelerates mobile data processing to allow carriers to deploy next generation applications to support massive data growth.
Software and Tools
LSI’s robust development tools and production quality data plane software accelerate time-to-market. The Axxia architecture’s scalability allows OEM software investment to be reused across the entire mobile network.

The Data Deluge: Mobile Network Challenges & Solutions [LSICorporation YouTube channel, Sept 18, 2012]

In this video, LSI President and Chief Executive Officer Abhi Talwalkar discusses the role of intelligent silicon in solving mobile network challenges.

Bridging the Data Deluge Gap–The Role of Smart Silicon in Networks [by Michael Merluzzi, LSI Corporation in EETimes Design, Feb 28, 2013]

The proliferation of smart mobile devices, video, user-generated content and social networking, and the rising adoption of cloud services for both enterprise and consumer services are all driving explosive growth of wireless networking infrastructure. Globally, mobile data traffic is expected to grow 18-fold between 2011 and 2016, reaching 10.8 exabytes per month by 2016. Today, video traffic alone accounts for 40 percent of the wireless network load. The number of mobile devices connected to wireless networks will reach 25 billion, averaging 3.5 devices for every person on the planet, by 2015. That number is expected to double, to 50 billion, by 2020.This growth in storage capacity and network traffic is far outstripping the infrastructure build-out required to support it, a phenomenon known as the data deluge gap.
To bridge this gap, the industry needs to leverage smarter silicon technology to scale datacenter infrastructures more cost effectively. Besides helping close the data deluge gap, smarter data processing offers potential dramatic improvements in application performance. A recent survey of 412 European datacenter managers conducted by LSI revealed that while 93 percent acknowledged the critical importance of improving application performance, a full 75% do not feel that they are achieving the desired results. This indicates that there is rising pressure on datacenter managers to find smarter ways to push systems to do much more work within the same power and cost profiles.
Accelerating Networks
Smart software running on general-purpose processors, increasingly with multiple cores, is pervasive in the datacenter. Processors have long inhabited switches and routers, firewalls and load-balancers, WAN accelerators and VPN gateways. None of these systems are fast enough, however, to keep pace with the data deluge on its own, for a basic reason: general-purpose processors must treat every byte equally. While such equality is perfectly acceptable for system-level versatility, it is inadequate for low-level, high-volume packet processing.
This reality is driving the need for more intelligence in silicon that is purpose-built for specific networking applications to provide the right balance of performance, power consumption and programmability. Today’s smart silicon has reached a level of price/performance that makes it more cost-effective than adding general-purpose processors.
The latest generation of smart silicon typically features multiple cores of general-purpose processors and multiple acceleration engines for common networking functions, such as packet classification with deep packet inspection, security processing, especially for encryption and decryption, and traffic management.
Some of these acceleration engines are so powerful they can completely offload specialized network processing from general-purpose processors, making it easier to perform switching, routing and other networking functions entirely in smart line cards installed in servers and networking appliances to further accelerate overall network performance.
In many organizations today, microseconds matter, driving strong demand for faster response times. For trading firms, latency can be measured in millions of dollars per millisecond. For others, such as online retailers, every millisecond of delay can mean lost sales and fading customer loyalty. Tomorrow’s datacenter networks will need to be both faster and flatter, and therefore, smarter than ever. To eliminate the data deluge gap and maximize performance, systems need to be smarter, and those smarts will increasingly need to take the form of purpose-built silicon.
About the Author
Michael Merluzzi is product marketing manager in the Networking Solutions Group of LSI Corporation. Focusing on mobile backhaul applications, Merluzzi is responsible for marketing of integrated platform solutions and application-enabling software for the LSI Axxia family of multicore communication processors. Previously, he held a variety of roles in technical marketing, applications engineering and software development. Merluzzi holds a bachelor’s degree in Electrical Engineering from The Pennsylvania State University and master’s degrees in Business Administration and Computer Engineering from Lehigh University.

SoCs with more powerful cores need a more powerful interconnect [New Electronics, Jan 8, 2013]

… Troy Bailey is director of marketing with LSI. He said the company is seeing a ‘data deluge. “There is more and more data driven by video and mobile use. By most projections, the amount of data will outstrip the capacity of the infrastructure in the future, so what’s needed is faster devices to handle more data.”
Bailey also says there is a need for smarter devices. “We have to develop better ways to handle data; for instance, not moving data that doesn’t need to be moved. One of the ways we can do that is to add intelligence and processing throughout the network, rather than at gateways.”


The way to do this, in LSI’s opinion, is to add more and faster general purpose cores to network processors, but also to add acceleration engines to do those tasks with which general purpose cores struggle. “For example,” Bailey said, “there’s a lot of activity on a per packet basis – classifying, deep packet inspection. If you do these tasks with a general purpose processor, it will be slow and expensive.”
He has an analogy: “A mechanic with a basic set of tools can fix your car, but a specialist who works on one part of the car will have special tools and special knowledge.”
But, as he noted, traffic management is an important element in designing the architecture of a network processor. “If you can avoid sending data over the network, you’re better off and particularly so if you can cache it or put processing capacity closer to the network edge.”
LSI has a range of devices either available or in the planning stage. “We have single and dual core devices that perform the same tasks,” Bailey explained, “but we also have devices with dozens of cores. We see a strong opportunity to handle data in special purpose hardware, so devices will have more engines and more cores. This will need a balance between general purpose and special hardware.”
And the question of which cores to use has been under discussion. Until recently, LSI has based its network processors on PowerPC cores, but an announcement early in 2012 revealed ARM cores are now on the road map. “Some of these discussions are driven by customer requirements,” Bailey said. “The ARM architecture is strong and there’s a good ecosystem, so the move makes a lot of sense. LSI’s approach is based on hardware acceleration, which also makes sense, and we are not looking to use proprietary cores. So while a Cortex-A15 doesn’t necessarily bring more performance, it is more power efficient.”
Then comes the challenge of linking all these cores together. And LSI has turned again to ARM, taking a lead license for ARM’s CCN-504 interconnect. “We have helped ARM to define what’s required in such an interconnect. As you add more cores – particularly accelerators – you end up with a lot of compute elements and when that happens, there’s opportunities for bottlenecks. You could end up adding more cores, but getting lower performance,” Bailey contended.


Neil Parris is ARM’s interconnect product manager. He said CCN-504 had been developed specifically to address the issue of more cores. “It’s about providing coherency between the cpus and the I/O and about using data on chip.”
In some respects, it’s a consequence of integration. “There used to be a range of chips which needed to be connected,” Parris observed. “Now, it’s a single chip with multiple cores which is power critical and which needs to interface to the latest technology.”
CCN-504 – CCN stands for cache coherent network – is the first in a family of interconnects being developed to support future complex devices. “It supports four cpu clusters,” Parris said, “and each cluster can comprise up to four cores. It also supports ARM’s 64bit architecture, which is important for those people building servers.
“Each cpu cluster has an L2 cache, which is configurable to 2Mbyte, or 4Mbyte in the case of the Cortex-A15. The interconnect’s purpose is to join all the processors in a coherent manner, making sure all cores have a consistent view of memory.”
But CCN-504 isn’t ARM’s first cache coherent network. “That was the CCI-400,” Parris said. “That’s aimed at mobile applications with two clusters, including Big.LITTLE.”
Caching is an important element and one which supports Bailey’s view that you shouldn’t have to move data if you don’t have to. “Caches are important contributors to power efficiency and performance,” Parris pointed out. “The more data you have on chip, the fewer the accesses needed to external memory. It helps with power consumption and performance.”
CCN-504 has also been built with cores other than ARM’s in mind. The network can support up to 18 AMBA interfaces, which allows designers to take advantage of such functions as 40Gbit Ethernet, USB and serial ATA links. But it also features PCI-Express connectivity. “Companies will use this facility to add their own IP into an SoC,” Parris explained. “For example, they may wish to add their own accelerator, and it’s our aim to provide them with a scalable platform on which they can build.”
All 18 AMBA interfaces are connected to the cache coherent network through an I/O virtualisation block which provides unified system memory. “AMBA defines interconnect,” Parris said, “and CCN-504 builds on the AMBA interconnect. It has an integrated L3 cache, which can be configured from 8 to 16Mbyte, and a snoop filter.” The snoop filter basically keeps an eye on all caches to ensure coherency and reduce bus traffic.
If the SoC does need to access external memory, ARM has developed the DMC-520 memory controller for 72bit wide DDR3/4. This supports a maximum bandwidth of 25.6Gbyte/s per channel and features buffering to optimise reads and writes. It’s the fifth generation DMC and includes error checking and correction features.
Overall, CCN-504 supports a system bandwidth of around 1Tbit/s and operates up to the cpu clock rate. “This network scales the performance of the CCF400 significantly,” Parris noted, “with more ports and a larger cache. At the moment, it’s 128bit wide, but future devices will move up, including bandwidth,” he added.
Bailey said LSI needed a strong technology partner for interconnect. “It’s not our point of differentiation,” he said, “so the licensing approach made sense. When you think of an SoC with 16 cores, there may be a total of 30 compute elements. It’s a complex design and that’s why it needs a robust networking solution.”

4G World 2012: The Future of LTE [LightReadingTV YouTube, Nov 2, 2012] (on an Oct 29 – Nov 1 conference “where enterprises and operators met to discuss the state of the art of the mobile enterprise marketplace” [as per the announcement])

A panel on what the next three years will look like: – Simon Stanley, Senior Analyst, Heavy Reading as moderator – Asok Chatterjee, Vice President, Ericsson; Chairman, 3GPP Project Coordination Group – Stephen Turnbull, Division Marketing Manager, Freescale Wireless Access Division, Freescale – Noy Kucuk, Vice President of Marketing, Networking Solutions Group, LSI at 4G World 2012, Oct 29 – Nov 1, Chicago

4G World 2012: The 4G Opportunity [LightReadingTV YouTube, Nov 2, 2012] (on the same Oct 29 – Nov 1 conference)

Neville Ray, CTO of T-Mobile USA, delivers keynote at 4G World in Chicago

4G World 2012: Innovation: Strategy, Technology & Collaboration [LightReadingTV YouTube, Nov 2, 2012] (on the same Oct 29 – Nov 1 conference)

Praveen Atreya, Verizon’s director of network technology and head of its LTE Innovation Center, delivers his keynote at 4G World in Chicago

4G World 2012: The 1-Gigabyte Revolution [LightReadingTV YouTube, Nov 2, 2012] (on the same Oct 29 – Nov 1 conference)

Bill Payne, Head of Advanced Technologies, CTO North America at Nokia Siemens Networks, speaks at 4G World in Chicago about “engagement economy” leading to the “1 GB per day revolution by 2020” for which there is the need to provide a 1000x increase in traffic throughput


Nokia Siemens Networks and LSI Collaborate on Wireless Infrastructure Solutions [LSI press release, Feb 21, 2013]

LSI® Axxia® platform and SoC capabilities contribute to
higher-performance mobile broadband solutions
Nokia Siemens Networks and LSI Corporation (NASDAQ: LSI) announced today a collaborative framework with ARM® processor based System-on-Chips (SoCs) that enable enhanced support for real-time performance, I/O optimization, robustness and heterogeneous operating environments on multi-core SoCs.
Nokia Siemens Networks is increasing investment in technology development in mobile broadband business and actively participating in Linaro Networking Group and to ARM ecosystem in general to enable better use of Open Source Linux®software and tools. This will both enhance performance of forthcoming base station BTS products as well as drive towards lower power consumption.
“LSI is very pleased to be collaborating with Nokia Siemens Networks on innovative mobile broadband solutions,” said Jim Anderson, general manager for LSI’s Networking Solutions Group. “The LSI Axxia line combines ARM processor cores with our unique Virtual Pipeline™ acceleration technology to create a platform for next-generation mobile broadband solutions and other applications. Our advanced software and emulation capabilities ensure accelerated time to market for our customers.”

Networking Leaders Collaborate to Maximize Choice, Performance and Power Efficiency [Linaro press release, Feb 20, 2013]

Industry leaders including AppliedMicro, ARM, Enea, Freescale®, LSI, MontaVista, Nokia Siemens Networks and Texas Instruments (TI) have formed a new group focused on accelerating Linux development for ARM processors in cloud and mobile infrastructure.
Linaro, the not-for-profit engineering organization developing open source software for the ARM® architecture, today announced the formation of the Linaro Networking Group (LNG) with twelve founding member companies including … <see above> … at the Embedded Linux Conference (ELC).
With ARM-based SoCs at the heart of the transformation occurring in cloud and mobile infrastructure applications such as switching, routing, base-stations and security, Linaro’s members are collaborating on fundamental software platforms to enable rapid deployment of new services across a range of converged infrastructure platforms. Developing the base platform for diverse and complex networking applications requires a significant amount of software that addresses common challenges. LNG will deliver this as an enhanced core Linux platform for networking equipment. …
Networking infrastructure is undergoing a transformation driven by the ramp in diverse data being moved through disparate networks to and from billions of diverse devices. The industry needs to simplify the management of the network as well as create new applications that will enable cloud service providers, carriers and others to reliably provide a great user experience across expanded mobility use cases and the increasing globally-connected intelligence of devices. Enterprises need to scale their networks and their network management capabilities to cope with these demands and also enable the rapid evolution of applications for new revenue-generating business models. LNG will accelerate this transformation through its initial focus on fundamental optimizations for use across all ARM-based networking infrastructure equipment.
An interim steering committee for LNG has been meeting since the end of 2012 and has agreed on four initial areas of work:
  1. Virtualization support with considerations for real-time performance, I/O optimization, robustness and heterogeneous operating environments on multi-core SoCs.
  2. Real-time operations and the Linux kernel optimizations for the control and data plane.
  3. Packet processing optimizations that maximize performance and minimize latency in data flows through the network.
  4. Dealing with legacy software and mixed-endian issues prevalent in the networking space.
Linaro expects initial software deliveries from the Linaro Networking Group during the first half of 2013 with on-going monthly releases thereafter.

LSI hopes to power mobile networks with ARM-based processors [CIO, Feb 19, 2013]

Chipmaker LSI is taking ARM-based processors to new frontiers with its upcoming AXM5500 family, which will be used in mobile base stations of all sizes.
From today’s smartphones, tablets and thin clients to tomorrow’s servers, ARM-based processors are powering a growing number of different devices, and if LSI is successful, mobile networks will be added to that list. The company’s AXM5500 family of processors will use up to 16 Cortex-A15 cores to power base stations for mobile networks.
The Cortex-A15 is ARM’s most powerful processor to date, and is used in products like the Nexus 10 tablet from Google and Samsung Electronics.
“The intention is to provide high-performance and good efficiency on a scalable platform,” said Troy Bailey, director of marketing at LSI.
LSI’s processors for wireless infrastructure have historically been based on PowerPC processors, but because of increased demand for different size base stations in so-called heterogeneous networks, it decided to add ARM-based products.
In addition to achieving a new level of efficiency, working with ARM allows LSI to build a processor family that can be used in anything from a macro cell down to a pico cell, which means lower development costs, because software can be reused, according to Bailey. Pico cells are used to provide coverage for areas such as offices and shops. Installation and management becomes easier, as well, Bailey said.
The first two products are AXM5516 and AXM 5512, which have 16 and 12 cores, respectively. They are intended for use is large base stations. LSI will in the future add processors with fewer cores that are a better fit for small cells.
The product family also uses ARM’s new CoreLink CCN-504 Cache Coherent Network interconnect, which was announced in October last year. It can prioritize time-sensitive traffic and offers up to one terabit of usable system bandwidth per second, according to ARM.
“It is a very good and scalable interconnect. One of the challenges when building high core count processors is making sure you have no bottlenecks and waste the cores,” Bailey said.
The company is also looking at ARM’s new big.LITTLE processing architecture, which in its first generation combines the powerful Cortex-A15 and the energy-efficient Cortex-A7 on one die.
“There certainly are some tasks that need a very strong single thread performance, and there are some tasks that don’t, and it doesn’t make sense to light up a big A15 if it can be done on an A7, so we think it makes sense,” Bailey said.
The company will start sampling the first processors during the third quarter. Because the products aren’t being sampled yet, LSI will have to make to with visual demos showing the performance and power savings at next week’s Mobile World Congress.
LSI will have to convince equipment vendors that using ARM in their base stations is a good move and at least one company is open to the idea. Ericsson isn’t currently using ARM-based processors in its base stations. But “as we continue to expand and develop our base station portfolio, we always evaluate what possibilities are available from the general ICT industry and we might use ARM based processors in the future,” a spokeswoman said via email.
“We definitely have some major customers that are going in the ARM direction, and we have built this product for them” Bailey said.

More media reports for general briefings:
ARM Chips Take on New Cellular Chores, Aided by LSI [Digits blog of WSJ, Feb 19, 2013]
ARM is already the brains of your smartphone. Now it wants to run the network too  [GIGAOM, Feb 20, 2013]


Understanding LSI
[LSICorporation YouTube channel, Dec 19, 2012]
[10:43] In the case of wireless infrastructure we are engaged with all the system providers . But what’s also exciting we’re engaged deeply with the top two players. This is Ericsson as well as Nokia-Siemens who have between the two of them 50 to 60% share in the wireless infrastructure market. [11:02]

Learn how LSI is helping companies address and take advantage of today’s constantly growing data volumes.

See also: Investor Relations Update [LSI Corporation, Jan 23, 2013] from which the following three slides provide the latest relevant information:

Note: SAM (Served Available Market or Segmented Addressable Market) is a term that is typically used to reference the customers that can actually be reached out of the TAM (Total Addressable or Available Market). More on that: Estimate Addressable Market, Defining your TAM, Total Addressable Market and  The importance of TAM, SAM and SOM in your plan imageimage
LSI Management Discusses Q4 2012 Results – Earnings Call Transcript [Jan 23, 2013]: We began ramping our standard product Axxia multi-core communication processor at the leading base station OEM and expect continued growth as we move through this year. We have multi-generational engagements in the wireless space that we believe will enable LSI to have in excess of 50% share in data and control plane processing silicon in a few years. In addition to standard products like Axxia, we have custom silicon wins in the baseband function of base stations with multiple OEMs, further broadening LSI’s footprint in base station infrastructure. … We feel very good about our growth initiatives across networking. Axxia and our multi-core solution there continues to be adopted more and more across base station system vendors.image
LSI’s CEO Presents at Morgan Stanley Technology, Media & Telecom Conference (Transcript)
[Feb 26, 2013]: We made a major announcement last week with Nokia Siemens. Nokia Siemens and LSI are collaborating on LSI’s next-generation Axxia processor. It’s the industry’s first 16-core ARM network processor. We believe we’ll have at least a 9- to 12-month advantage relative to time to market, as well as the attributes that we have in our product. This is a pretty significant achievement, with Nokia Siemens. It adds to the other major player that we’re also shipping Axxia into. And it’s a proof-point to what we said a year ago. We said a year ago that we would have over 50% share of the data plane and control plane, basically the CPU in the base station, that we would have 50% share over the course of the next several years. So we have 2 of the top 3 companies now adopting Axxia, and we’re well on our way to achieve that share position.
We also can extend that commentary into the baseband where we are also going to ship baseband silicon into these 2 companies, which we also believe will amount to at least 40% share. These share levels are up from 10% today. So we’re very excited about what’s happening in our networking business.

LSI transforming itself again [Brian Bailey on EETimes, Feb 20, 2013] (with the illustrations replaced by equivalent images from the AXM2502 Product Brief [March 8, 2012] and AXM5500 Product Brief [Feb 19, 2013] respectively which I recommend to read for further technical details)

LSI is a company that has been through a lot of changes over the years. I can remember when they had their own fabs, did custom design for their customers, and had their own suite of design tools. In short, they were a complete vertically integrated ASIC house. They have evolved many times and become fabless, transitioned to semi-custom design and today is building standard parts for markets such as storage and wireless networking.

The other day we learned about another big change in LSI future and it all has to do with their Axxia line of communications processors. Take a look at the block diagram for the AXM2502 product. It was powered by a pair of PowerPC processors connected to custom accelerators using their Virtual Pipeline technology. This is a 28nm product.


This week, LSI introduced the Axxia 5500 product family of communication processors designed to accelerate performance and increase power efficiency for multi-radio base stations and 4G/LTE-capable wireless networks. The LSI Axxia 5500 product family features 12 or 16 ARM cores.


This switch in processing core brings about a 4X control plane performance improvement and 2,5X data plane improvement and reduced power – something that is becoming important for all applications from battery powered handhelds to datacenters.

This chip not only makes advances for LSI, but ARM also. The two companies partnered to create this 16 core solution utilizing ARMs new CoreLink CCN-504 interconnect. CoreLink CCN-504 can deliver up to one Terabit of system bandwidth per second.

LSI also provides much of the software necessary to power this chip including high-performance layer two through four software packages that provide a complete wireless transport solution for networking OEMs.

More 3d party reports for further technical briefings:
LSI and 6WIND team up for high performance networking [SemiAccurate, Oct 16, 2012]
How does LSI envision the next generation of ARM networking SoCs? [SemiAccurate, Nov 28, 2012]
LSI launches a 16-core ARM A15 cell phone chip [SemiAccurate, Feb 19, 2013]

The HetNet problem as LSI sees it

Until recently, you needed very different devices from top to bottom, the hardware on a pico basestation was nothing like that of the vastly larger long distance stations. This mandates some very different software stacks, management tools, and all sorts of other things that bring problems to the poor network trolls running the plumbing 24/7. Heterogeneity is not a good thing here, but there really wasn’t a choice, no hardware was suited for all of the tasks at hand. See what LSI is aiming for now?

Since the Axxia 5500 line can scale from 4 to 32 cores, it can meet all of the demands of basestations large and small. If the pico basestation needs a digitial front end and DSP setup that the big ones don’t, no problem, slap them on. If there are things that the little ones don’t need, pull them out and save die area. LSI hopes to be able to service all of a carrier’s needs from large to small with a single hardware family and the attendant software stack. Carriers like this, it saves them time, money, and headaches, speeds deployment, and makes life easier by simplifying everything. And that is exactly what LSI is aiming for with the Axxia 5500 family.

Corresponding LSI press releases with more information:
LSI Announces Availability of Family of Network Accelerator Cards for Enterprise, Data Centers and Service Providers [July 20, 2011] “Complete platform built on industry-leading silicon with software protocols to provide high performance and deterministic features for networking OEMs
LSI Begins Shipping 28nm Custom Silicon for Datacenter and Mobile Network Applications [Nov 16, 2011] “Custom silicon enables networking and storage OEMs to build highly differentiated silicon solutions; demonstrates LSI leadership
LSI Expands Strategic Relationship with ARM to Offer Energy-Efficient Multicore Processors for Networking Applications [Jan 23, 2012] “Enhances industry’s most powerful networking silicon portfolio … LSI will gain access to:

  • The broad family of ARM processors, including the ARM Cortex-A15 processor with virtualization support and future ARM processor
  • ARM on-chip interconnect technology, including CoreLink™ cache coherent interconnect system IP, for use in multicore applications”

LSI Introduces Highly Integrated Axxia Communication Processor to Accelerate Mobile Broadband [Feb 21, 2012] “AXM2500 reduces power consumption and physical space requirements; helps service providers seamlessly deploy heterogeneous networks and contend with data growth
LSI Expands Axxia Platform to Deliver Power-Efficient Mobile Networks [Feb 23, 2012] “Addition of ARM’s latest multicore technology will provide scalability, performance and low power consumption to meet growing demand for mobile broadband
LSI Expands Networking Ecosystem to Accelerate Implementation of 4G Networks [Feb 24, 2012] “Partner solutions accelerate time to market and reduce software investment for wireless manufacturers
LSI Collaborates with Vineyard Networks to Accelerate Mobile and Datacenter Networks [May 7, 2012] “Vineyard joins LSI networking ecosystem; combined solution delivers real-time application recognition to improve user experience
LSI and Microsemi Collaborate to Reduce Costs and Increase Performance of Mobile Networks [Sept 19, 2012] “Integration of Microsemi timing protocol into LSI® Axxia®communication processors provides networking equipment manufacturers with increased interoperability, reduced customer investment and faster time-to-market
LSI and 6WIND Team Up to Accelerate Mobile Infrastructure and Datacenter Network Performance [Oct 16, 2012] “6WINDGate packet processing software for LSI® Axxia®platform allows network OEMs to benefit from performance-optimized software that reduces time-to-market and lowers development costs
LSI Summit Convenes Technology Leaders to Unlock Opportunities in the New Innovation Era of Devices, Datacenters and Mobile Networks [Nov 13, 2012] “5th annual ‘Accelerating Innovation Summit’ attracts storage and networking experts to collaborate on solving the challenges of the data deluge
LSI Introduces Axxia® 5500 Communication Processors with ARM Technology for High-Performance, Power-Efficient Networks [Feb 19, 2013] “LSI scalable architecture with ARM multicore processors and interconnect to improve multi-radio base station and 4G/LTE-capable wireless network performance

Future Coherent Interconnect Technology for Networking Applications [ARM’s Smart Connected Devices blog, Dec 11, 2012]

Coherent interconnects will be at the core of next-generation network systems and system-on-chip (SoC) devices. To meet the rapidly growing processing requirements of wireless infrastructure systems and servers, network equipment manufacturers need highly integrated SoCs with a heterogeneous mix of CPU cores. These cores need to handle a mix of general-purpose processing, packet processing and digital signal processing (DSP) functions. The interconnect at the center of these solutions must maintain cache coherency between cores and provide a low-latency path between the cores, caches, external memory and networking I/O.
We are seeing dramatic growth in the data bandwidth in both mobile and fixed line networks. Cloud computing and video services are key applications driving this growth. 4G/LTE networks are transforming the wireless network experience for high-volume data users. Larger data centers with many virtualized servers allow large content providers such as Facebook, Google and Amazon to support many millions of users. To meet these demands, carriers are making significant investments in enhanced 4G networks and infrastructure required to support the huge growth in data traffic.
The latest silicon technology allows the integration of many cores onto a single SoC, dramatically reducing the number of components in a system. The processor cores can be closely coupled to hardware acceleration engines, external memory interfaces and high-speed networking I/O. The level of integration presents significant challenges to developers, who must ensure the use of shared resources does not reduce system performance. The key to this integration is the interconnect between the different cores and the other functional blocks.
Standard RISC cores, licensed from vendors such as ARM, have allowed system OEMs to quickly develop new solutions using third-party tools for software development. The introduction of licensed IP for a low-latency coherent interconnect will allow OEMs to develop more easily new solutions integrating multiple general purpose CPU and other cores. By working with well-established IP and SoC vendors such as ARM and LSI, system developers will have access to next-generation networking SoCs with a mix of CPU cores, hardware accelerators and, if required, their own hardware blocks.
The “Future Coherent Interconnect Technology for Networking Applications,” by Heavy Reading for LSI and ARM, explores the benefits of using a low-latency, coherent interconnect at the core of a next-generation networking SoC and reviews the market demand for next-generation network SoCs with multiple CPU cores and hardware accelerators. It details the technical challenges and one solution that is available to system developers for a coherent interconnect with integrated cache and support for DDR3 and DDR4 memories. The paper also describes a next-generation networking SoC architecture that is built around a coherent interconnect and available to OEMs as a standard product or custom solution.
Guest Partner Blogger:
imageMichael Merluzzi is a Sr. Marketing Manager in the Networking Solutions Group at LSI Corporation. He has product marketing responsibilities for integrated platform solutions and application-enabling software for LSI’s Axxia® family of multicore communications processors. Previously, he has held a variety of roles in technical marketing, applications engineering and software development.
Michael holds a bachelor’s degree in Electrical Engineering from the Pennsylvania State University and master’s degrees in Business Administration and Computer Engineering from Lehigh University.

Next-Generation Multicore ARM Architectures for Intelligent Networks:






Next-generation multicore SoC architectures for tomorrow’s communications networks [by David Sonnier, LSI Corporation on Embedded Computing Design, Dec 11, 2012]

IT managers are under increasing pressure to boost network capacity and performance to cope with the data deluge. Networking systems are under a similar form of stress with their performance degrading as new capabilities are added in software. The solution to both needs is next-generation System-on-Chip (SoC) communications processors that combine multiple cores with multiple hardware acceleration engines.
The data deluge, with its massive growth in both mobile and enterprise network traffic, is driving substantial changes in the architectures of base stations, routers, gateways, and other networking systems. To maintain high performance as traffic volume and velocity continue to grow, next-generation communications processors combine multicore processors with specialized hardware acceleration engines in SoC ICs.
The following discussion examines the role of the SoC in today’s network infrastructures, as well as how the SoC will evolve in coming years. Before doing so, it is instructive to consider some of the trends driving this need.
Networks under increasing stress
In mobile networks, per-user access bandwidth is increasing by more than an order of magnitude from 200-300 Mbps in 3G networks to 3-5 Gbps in 4G Long-Term Evolution (LTE) networks. Advanced LTE technology will double bandwidth again to 5-10 Gbps. Higher-speed access networks will need more and smaller cells to deliver these data rates reliably to a growing number of mobile devices.
In response to these and other trends, mobile base station features are changing significantly. Multiple radios are being used in cloud[]-like distributed antenna systems. Network topologies are flattening. Operators are offering advanced Quality of Service (QoS) and location-based services and moving to application-aware billing. The increased volume of traffic will begin to place considerable stress on both the access and backhaul portions of the network.
Traffic is similarly exploding within data center networks. Organizations are pursuing limitless-scale computing workloads on virtual machines, which is breaking many of the traditional networking protocols and procedures. The network itself is also becoming virtual and shifting to a Network-as-a-Service (NaaS) paradigm, which is driving organizations to a more flexible Software-Defined Networking (SDN) architecture.
These trends will transform the data center into a private cloud with a service-oriented network. This private cloud will need to interact more seamlessly and securely with public cloud offerings in hybrid arrangements. The result will be the need for greater intelligence, scalability, and flexibility throughout the network.
Moore’s Law not keeping pace
Once upon a time, Moore’s Law – the doubling of processor performance every 18 months or so – was sufficient to keep pace with computing and networking requirements. Hardware and software advanced in lockstep in both computers and networking equipment. As software added more features with greater sophistication, advances in processors maintained satisfactory levels of performance. But then along came the data deluge.
In mobile networks, for example, traffic volume is growing by some 78 percent per year, owing mostly to the increase in video traffic. This is already causing considerable congestion, and the problem will only get worse when an estimated 50 billion mobile devices are in use by 2016 and the total volume of traffic grows by a factor of 50 in the coming decade.
In data centers, data volume and velocity are also growing exponentially. According to IDC, digital data creation is rising 60 percent per year. The research firm’s Digital Universe Study predicts that annual data creation will grow 44-fold between 2009 and 2020 to 35 zettabytes (35 trillion gigabytes). All of this data must be moved, stored, and analyzed, making Big Data a big problem for most organizations today.
With the data deluge demanding more from network infrastructures, vendors have applied a Band-Aid to the problem by adding new software-based features and functions in networking equipment. Software has now grown so complex that hardware has fallen behind. One way for hardware to catch up is to use processors with multiple cores. If one general-purpose processor is not enough, try two, four, 16, or more.
Another way to improve hardware performance is to combine something new – multiple cores – with something old – Reduced Instruction Set Computing (RISC) technology. With RISC, less is more based on the uniform register file load/store architecture and simple addressing modes. ARM, for example, has made some enhancements to the basic RISC architecture to achieve a better balance of high performance, small code size, low power consumption, and small silicon area, with the last two factors being important to increasing the core count.
Hardware acceleration necessary, but …
General-purpose processors, regardless of the number of cores, are simply too slow for functions that must operate deep inside every packet, such as packet classification, cryptographic security, and traffic management, which is needed for intelligent QoS. Because these functions must often be performed in serial fashion, there is limited opportunity to process them simultaneously in multiple cores. For these reasons, such functions have long been performed in hardware, and it is increasingly common to have these hardware accelerators integrated with multicore processors in specialized SoC communications processors.
The number of function-specific acceleration engines available also continues to grow, and more engines (along with more cores) can now be placed on a single SoC. Examples of acceleration engines include packet classification, deep packet inspection, encryption/decryption, digital signal processing, transcoding, and traffic management. It is even possible now to integrate a system vendor’s unique intellectual property into a custom acceleration engine within an SoC. Taken together, these advances make it possible to replace multiple SoCs with a single SoC in many networking systems (see Figure 1).
imageFigure 1: SoC communications processors combine multiple general-purpose processor cores with multiple task-specific acceleration engines to deliver higher performance with a lower component count and lower power consumption.
In addition to delivering higher throughput, SoCs reduce the cost of equipment, resulting in a significant price/performance improvement. Furthermore, the ability to tightly couple multiple acceleration engines makes it easier to satisfy end-to-end QoS and service-level agreement requirements. The SoC also offers a distinct advantage when it comes to power consumption, which is an increasingly important consideration in network infrastructures, by providing the ability to replace multiple discrete components in a single energy-efficient IC.
The powerful capabilities of today’s SoCs make it possible to offload packet processing entirely to system line cards such as a router or switch. In distributed architectures like the IP Multimedia System and SDN, the offload can similarly be distributed among multiple systems, including servers.
Although hardware acceleration is necessary, the way it is implemented in some SoCs today may no longer be sufficient in applications requiring deterministic performance. The problem is caused by the workflow within the SoC itself when packets must pass through several hardware accelerators, which is increasingly the case for systems tasked with inspecting, transforming, securing, and otherwise manipulating traffic.
If traffic must be handled by a general-purpose processor each time it passes through a different acceleration engine, latency can increase dramatically, and deterministic performance cannot be guaranteed under all circumstances. This problem will get worse as data rates increase in Ethernet networks from 1 Gbps to 10 Gbps, and in mobile networks from 300 Mbps in 3G networks to 5 Gbps in 4G networks.
Next-generation multicore SoCs
LSI addresses the data path problem in its Axxia SoCs with Virtual Pipeline technology. The Virtual Pipeline creates a message-passing control path that enables system designers to dynamically specify different packet-processing flows that require different combinations of multiple acceleration engines. Each traffic flow is then processed directly through any engine in any desired sequence without intervention from a general-purpose processor (see Figure 2). This design natively supports connecting different heterogeneous cores together, enabling more flexibility and better power optimization.
imageFigure 2: To maximize performance, next-generation SoC communications processors process packets directly and sequentially in multiple acceleration engines without intermediate intervention from the CPU cores.
In addition to faster, more efficient packet processing, next-generation SoCs also include more general-purpose processor cores (to 32, 64, and beyond), highly scalable and lower-latency interconnects, nonblocking switching, and a wider choice of standard interfaces (Serial RapidIO, PCI Express, USB, I2C, and SATA) and higher-speed Ethernet interfaces (1G, 2.5G, 10G, and 40G+). To easily integrate these increasingly sophisticated capabilities into a system’s design, software development kits are enhanced with tools that simplify development, testing, debugging, and optimization tasks.
Next-generation SoC ICs accelerate time to market for new products while lowering both manufacturing costs and power consumption. With deterministic performance for data rates in excess of 40 Gbps, embedded hardware is once again poised to accommodate any additional capabilities required by the data deluge for another three to four years.
David Sonnier is a technical fellow in system architecture for the Networking Solutions Group of LSI Corporation.
LSI Corporation david.sonnier@lsi.com www.lsi.com

See how innovative is the Axxia SoC networking platform for mobile broadband speed [LSI China, Oct 15, 2012] as translated from Chinese by Google (except the introductory summary which manual corrections as well) because there is no English equivalent

What is Axxia? A communication processor? Not only that! It represents a unique innovation network SoC solutions platform, flexible and energy efficient and scalable architecture! It contains the complete network chip and software combination:
  1. Communication processor, using state-of-the-art multi-core technology which can achieve fast path acceleration with deterministic performance and highly programmable;
  2. Highest density, lowest cost and fully programmable media and baseband processor;
  3. The TDM (time-division multiplex) transport of multiservice processor, high-density, low-power and fully trust through the packet network;
  4. Customizazion based on Axxia processors, flexible customer management, industry-leading delivery times.
The Axxia Network SoC solutions for mobile and enterprise networks determine performance, customized solutions to achieve a high degree of differentiation.
Flexible and highly scalable platform
<from here on raw Google translation>
“With the mass deployment of EVS, SAE and LTE-Advanced, the new architecture of the system on the network bandwidth requirements will far exceed the processing capacity of the current infrastructure, which requires the SoC architecture with excellent expansion capability, in order to effectively control costs , while responding to the ever-rising demand for bandwidth. “LSI corporate network components, marketing director Tareq Bustami has pointed out.
Axxia the use of energy-efficient central processing unit (CPU) platform and instruction set architecture (ISA) multicore architecture-independent, allowing the general-purpose processor with flexible, determined by the Virtual Pipeline high-speed path integration, for according to the specific needs of the OEM manufacturers extend and customize Axxia platform to choose their own silicon design, such as ASIC, CSSP or ASSPs. Unique business model is the LSI customers widely hailed (as shown in Figure 1).
Figure 1. The LSI Axxia network platform has an original mixed approach of the general and specific types of processing, and has the ability to integrate custom IP.
This flexible business model is built on the LSI IP accumulation basis. Customers comply with the standards provided by LSI pre-verified IP cores to reduce costs and accelerate time-to-market.
CoreWare IP in LSI the proven complex IP functionality, and to achieve specific LSI design integrity, ease of use, reusability, supportability, quality, range of standard deliverables and supporting infrastructure. , CoreWare IP address program leading storage industry standard interfaces and components are synergistic, ensure compliance, and customer resources to focus on product differentiation and competitive advantage.
Since 1990 LSI IP solutions already contains a high-level, pre-packaged chip components and complete delivery, the LSI leading design tools and methods to achieve integration. LSI IP support for system-level design considerations for end-use applications, including simulation and signal integrity requirements.
LSI also provides a flexible IP subscription model, allowing customers to choose a wide range of solutions from LSI, from the the SerDes or I / O unit to complete the I / O controller, processor subsystem processor core to complete. Specifically including but not limited to: 1. (Key storage and network interface) from the current and next generation serial standards support, such as XFI (10G), Fibre Channel (8.5G), SAS (6G), PCI Express (5G) as well as many other interfaces; 2. the latest parallel storage interface supports DDR3 SDRAM, QDR, DDR II + SRAM and RLDRAM; memory chip-to-chip interface, such as SGMII and SPI4; 3. supports the industry’s most popular integrated processor products, such as PowerPC, ARM, MIPS and ZSP.
Collaboration with ARM, significantly improve mobile network performance / power ratio
Particularly worth mentioning is the integration, in addition to continue to develop Axxia communication processors, high-performance multi-core PowerPC-based ASSP products, LSI also recently a new high-performance multi-core ARM Cortex A-15 processor and LSI hardware accelerators certainty The Axxia processor program series ASSPs ideal for mobile access, backhaul and gateway. The series offers a variety of pin-compatible configuration, suitable for a variety of network applications, NodeB and eNodeB 3G/4G mobile access to the system, the mobile broadband radio network controller (RNC) applications as well as enterprise gateway. The Axxia Series provides a comprehensive software development environment, evaluation board, as well as the industry’s leading supplier, launched a series of hardware / software solutions.
ARM CPU and LSI hardware accelerators with the the Virtual Pipeline patented technology to achieve the best performance and flexibility. This partnership to provide customers with a proven scalable, multi-function software platform to support the extended multi-generation wireless infrastructure. LSI has been a long history of cooperation with ARM kernel currently has shipped over one billion ARM core integrated into LSI flagship the Axxia platform is a natural choice. The platform enables wireless manufacturers to develop a solution that contains all base station processing functions.
Add the ARM energy saving core the Axxia platform can base stations and wireless infrastructure to provide energy-efficient, low-power multi-core processors; provide scalable performance to meet smart phones, tablet PCs and cloud services bring massive data growth needs; embedded intelligence, can be used to determine flow, identification applications, provide appropriate traffic and at the right time in order to achieve real-time services such as mobile video. Through the the ARM Community and LSI network ecosystem, customers also have access to a wealth of third-party tools and support.
The innovative Virtual Pipeline patented technology to determine performance
Any routing combination of LSI Virtual Pipeline (Virtual Pipeline) patented technology developed for each packet classification decisions, each data packet or communications media stream prior to leaving the ACP can after engine CPU core. This flexibility is very powerful and convenient, and is conducive to the design of traffic flowing through the device.
Using patented technology hardware scheduler function with any-to-any data packet streaming combined, and thus needed to route traffic on-chip, able to achieve in the the acceleration engine multicore Commonwealth SoC subsystem components between smooth Communication chip. The flow from the input port is routed directly to the hardware acceleration engine, and then routed to the next acceleration engine, transmission path depends entirely on the processing requirements of specific traffic, regardless of whether or not to use the CPU core. Can achieve up to 20Gbps or more deterministic data throughput, and to achieve deterministic transmission and L2 performance in a longer transition period may be well suited for multi-protocol processing applications.
Figure 2. Virtual Pipeline message transmission of the highly innovative patented technologies.
For example, through the Virtual Pipeline patented technology can be first Ethernet interface receives traffic sent to the decryption engine to decrypt the encrypted traffic, and then routed directly to the content inspection engine contain viruses / spam or other malicious content traffic filtering. If the flow is considered safe, can be directly transmitted to the rear panel ports, without going through the CPU core. In addition, we also needed to flow from the input port or accelerate the engine is routed to the CPU core for further processing.
Wireless eco-system platform to reduce costs, accelerate time to market
Mark Hung, research director at Gartner, said: “built under the premise of controlling costs to meet the growing demand for mobile broadband network, which is a big challenge. Operators will benefit from a higher degree of integration of the mobile infrastructure system IC solve program, because they cost the transition to 4G networks. “
As mentioned earlier, Axxia platform provide highly differentiated multi-core chip and software architecture can achieve scalability and identify performance benefits to customers include: capital expenditures can be reduced by 50%; while the power consumption improvements reduce power consumption by 50% reduction of operating costs; simplified software architecture cocoa to help customers reduce software development work; the active industrial environment can be enhanced debugging capabilities, thus speeding up the listing process; while a high level of system integration can reduce the cost of materials (such as memory and switch) ; uncertainty platform can also shorten the delay, to improve the user experience, and so on.
Figure 3: the Axxia wireless platform ecosystem including IP cores, OS platform and developer tools for ISVs, ODMs, CMs and other partners, providing a strong industrial environment of support.
As service providers compete to deploy 4G wireless infrastructure, LSI is bound growth expected customer demand for reliable integration solutions, was founded a few years ago a the Axxia wireless ecological system, combined with IP cores, operating systems and tools various partners, developers, independent software developers (ISVs), ODM, CM, to the advantage of price, performance, and flexible power range of products both Axxia series to help wireless equipment manufacturers to accelerate time to market, reduce software investment.
LSI and its ecosystem partners recently announced the plans of the wireless platform, pre-integrated solutions to provide optimal performance for their own the Axxia wireless platform to provide stronger support industrial environment. LSI ecosystem partners are encouraged to focus on the benefits of development features, and performance differentiation, rather than using a dedicated interface.
This wireless ecosystem platform provides a proven, scalable, multi-function software platform to support multiple generations of Axxia product line; consistent software architecture to simplify the customer transplantation of the the Axxia products enable customers to choose the best. Framework API LSI architecture oversight functions allow open access to different ecosystem partners.Ecosystem partners committed LSI architecture to optimize performance and support the strategic objectives of the wireless platform.
For example, LSI is in cooperation with the main partners in the the Axxia wireless industry environment Radisys Trillium 3G and LTE wireless protocol software specifically for the LSI Axxia platform integration and optimization. Axxia platform so that you can take advantage of a unique, scalable capacity and performance, simple and convenient to deploy the Radisys wireless software.
Such wireless ecosystem platform plans to help the wireless OEM manufacturers and their suppliers ecosystem response to earnings challenges, accelerate time to market, lower total cost of ownership.Reduce software investment to achieve higher performance of OTB. At the same time minimizing the cost of the non-differentiated products. Reduce technical barriers, you can choose more cost effective, lower power consumption optimal product!
(This article is LSI Corporation feed)

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