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TSMC led foundries and their SoC customers against Intel

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See also: Intel’s SoC strategy strengthened by 22nm Tri-Gate technology [May 10, 2011]

Follow-up: Next-gen Snapdragon S4 class SoCs — exploiting TSMC’s 28nm process first — coming in December [Aug 9 – Nov 25, 2011]

Update: TSMC seeing tight capacity for 28nm processes [Nov 25, 2011]

Taiwan Semiconductor Manufacturing Company (TSMC) continues to see orders heat up for advanced 28nm technology, despite a general slowdown in the semiconductor industry, according to industry sources. Order visibility has stretched to about six months, said the sources.

TSMC is expected to see 28nm processes account for more than 2% of company revenues in the fourth quarter of 2011. The proportion will expand further to over 10% in 2012, as more available capacity coupled with rising customer demand boost the output, the sources indicated.

Wafer output using 28nm processes is projected to top 20,000 units a month by the end of 2011, and will expand significantly in 2012 when new capacity at Fab 15 comes online, the sources noted. Fab 15, TSMC’s third 12-inch fab, will begin volume production in the first quarter of 2012, and ultimately raise its monthly capacity to the designed level of 100,000 wafers per month.

Altera, AMD, Nvidia, Qualcomm and Xilinx have all contracted TSMC to manufacture their 28nm products. Broadcom, LSI Logic and STMicroelectronics reportedly are among potential clients for TSMC’s 28nm technology.

TSMC chairman and CEO Morris Chang remarked during the company’s most-recent investors meeting that sales from 28nm process technology would play an important source of company growth.

TSMC to Double Output Capacity in Five Years [May 6, 2011]

Over the past three years, the No.1 silicon foundry spent around US$16 billion boosting production capacity, to an equivalent of 10 million 200mm wafers. The company`s four new factories will help achieve the 20 million wafer goal after entering into pilot production sometime this year.

Advanced process technologies are crucial in the goal. The company will put its 28nm process into pilot production at its Fab 15, an extraordinarily huge wafer fab by capacity, in the third quarter of the year. By the end of this year, the company`s 300mm wafer fabs are projected to have total output of 300,000 wafers of chips a month.

TSMC Estimated to Earn NT$7 Per Share in 2012 [May 10, 2011]

The No.1 silicon foundry recently announced it would enter pilot production based on 28nm process technology sometime in the third quarter ahead of schedule and kick off volume production in the following quarter. So far, the chipmaker has completed 89 contracted 28nm tapeouts, the final results of photomask design for 28nm integrated circuit.

Industry watchers pointed out that the tapeout number is 10 times the number of all its competitors and twice the number of the company`s 40nm tapeouts introduced in 2008. TSMC, they added, has seen hefty revenue and earnings from 40nm process, which it took two years to develop.

Some institutional investors noted that advanced process technologies have propelled TSMC far ahead of its rivals in market dominance, with 65nm process securing a 65% of the contracts depending on the process and 40nm wining an 80% of the customers using the process. Overall, TSMC has filled 47.1% of world demands for silicon foundry service.

They analyzed TSMC still gains an upper hand in 28nm competition in spite of formidable competitors as Intel and Samsung. These competitors would have an uphill battle against TSMC if they fail to put 28nm process into volume production by the end of this year.

Over the next three years, smartphone and tablet PC will remain the major drivers behind TSMC`s growth.
This year, TSMC has budgeted US$7.8 billion for boosting its 28nm, 40nm and 65nm production capacities, compared with its US$5.9 billion spending on advanced process projects last year.

TSMC Makes Fortune From Smart Phones [May 3, 2011]

For every smartphone sold on the market, Taiwan Semiconductor Manufacturing Co. (TSMC) rakes in an average of US$7 in revenue from the sale, the company`s chairman and chief executive officer, Morris Chang estimated.

TSMC has been the primary contract manufacturer of the chips for almost all smartphones other than iPhones. Its contract buyers include processor vendors Nvidia Corp., Texas Instruments Inc. (TI) and Marvell Technology Group Ltd. as well as wireless-chip vendors Broadcom Corp. and Qualcomm International Inc.

Thanks to a strong smartphone market, sales of contracted chips for communications products constituted 48% of TSMC`s revenue of NT$105.3 billion (US$3.5 billion at US$1: NT$30) for the first quarter.

TSMC to Launch 20nm Pilot Production in 2012 [April 26, 2011]

Taiwan Semiconductor Manufacturing Co. (TSMC) will put its 20nm process into pilot production sometime in the second half of 2012 as its first step into 450mm wafer era, according to the company`s senior vice president in charge of research and development, S.Y. Chiang.

The senior vice president disclosed the process-technology roadmap yesterday at a forum, held in Taipei, addressing very-large scale integration (VLSI) technology.

As for 28nm process technology, Chiang pointed out that the company, which is recognized as the world`s No.1 pure silicon foundry, will place the process on volume production lines in the second half of this year. The company has begun pilot run of this process technology in the second quarter of the year on some design tapeouts. Tapeout means the final step of IC design cycle at which the photomask of the IC is sent for manufacturing.

Chiang noted that 28nm process can turn out more than twice as many chips as 40nm can on the same wafer. He added the company will complete pilot production of the process on 70 tapeouts throughout this year.

Chiang estimated the Moore`s Law, which is named after Intel Co-Founder Gordon E. Moore describing the number of transistors in an IC chip will double about every 18 months since the 1965 invention of IC, will remain applicable in the semiconductor industry at least until 7nm process is introduced.

He said in the future wafer foundries will not only shrink chip size but also system-on-chip size and the room for size-shrinkage technology to advance will remain ample.

Also, the room for cooperation between silicon foundries and chip assemblers, Chiang added, will grow bigger when sizes of single chips and system chips continue scaling down.

UMC Scrambles to Boost 300mm Capacity to Combat Nearest Competitor [April 13, 2011]

United Microelectronics Corp. (UMC) plans to set aside nearly 90% of the US$1.8 billion it plans to spend on expansions this year for boosting capacities at its 300mm wafer fabs, in a bid to further stay ahead of the ambitious GlobalFoundires Singapore Pte. Ltd.

GlobalFoundries, currently the world`s No.3 pure silicon foundry next to Taiwan Semiconductor Manufacturing Co. (TSMC) and United Microelectronics Corp. (UMC), has vowed to soar past UMC as its primary goal. The company has budgeted US$5.4 billion for expansions this year in conjunction with its ambition.
GlobaFoundries plans to boost output at its 300mm fab each in New York, Singapore and Dresden to the maximum 190,000 wafers altogether a month by 2012.

UMC plans to boost output of 300mm wafers to 150,000 a month sometime in the second half of next year after ramping up to 100,000 by the end of this year. Although the volume is 40,000 wafers fewer than GlobalFoundires’, UMC`s outputs of 200mm wafers are 20-30% above GlobaFoundries’ 200mm wafer outputs.

Industry executives estimated UMC would offer 40-50% more 200mm wafers than the nearest rival as soon as it merges HeJian Technology (Suzhou) Co., Ltd.

The 28nm Turning Point [Tom R. Halfhill, The Linley Group, April 18, 2011]

Foundries Bring High-k Metal Gates to the Masses

Metal tools delivered humanity from the Stone Age, and now, metal is enabling another technological breakthrough. For the first time, metal-gate transistors are broadly available to chip designers, allowing them to create higher-performance microprocessors that can still occupy less silicon and consume less power. This nanoscale application of metallurgy has been touted as the biggest advance in electronics since the invention of planar integrated circuits.

As usual, Intel got there first. In 2007, Intel introduced the first microprocessors built in its new 45nm high-k metal-gate (HKMG) process. The company substituted hafnium dioxide for the transistor’s silicon-dioxide gate dielectric and replaced the polysilicon gate electrodes of NMOS and PMOS transistors with other metallic materials. Thanks to higher dielectric constants (k), these materials increased the gate capacitance without reducing the thickness of the dielectric, allowing the transistor to operate at higher currents when switched on and to leak less current when switched off. (See MPR 1/29/2007, “Intel Leads the Way for High-k.”)

The rest of the semiconductor industry has been waiting four years for the same technology. Now, the wait is over. At the 32/28nm node, the leading independent foundries are introducing their own HKMG processes, and their first 28nm HKMG chips are entering production this year. Chip designers can use HKMG to deliver higher performance (by driving more current into the transistors) or to save power (mainly by reducing static current leakage). Most designers want a little of both.

Now that almost all digital-semiconductor companies except Intel rely on independent foundries or technology consortiums for their IC-process development, the 32/28nm rollout makes HKMG available to the entire industry. But the corollary is that HKMG probably won’t alter the competitive balances between most semiconductor-product companies, for the same reason: the technology is available to everyone. Although Intel enjoyed a four-year head start, the competitor most affected was AMD, the only other major vendor of PC processors. For the most part, everyone else competes with each other and not with Intel, and they’re all getting HKMG at about the same time.

Instead, the biggest contest is shaping up between leading semiconductor foundries, specifically TSMC (which reaps more than three times the revenue of any competitor) and upstart GlobalFoundries. If one of them can ramp production and improve yields significantly better than the other at 32/28nm, the foundry business could look much different at the 22/20nm node and beyond, when even more exotic technology will arrive.

Microprocessor Report subscribers can access the full story (7 pages, 5 graphics) here:

FinFETs Extend Intel’s Technology Lead [Tom R. Halfhill of the Linley Gwennap Group, May 6, 2011] (emphasis is mine)

Cadillac introduced tailfins to evoke high-tech style in the 1950s, but Intel’s new finned transistors are far from cosmetic. Purely functional, highly efficient, yet equally brash, these fin-shaped field-effect transistors (finFETs) are sure to be copied as widely as Cadillac’s useless appendages—and they will play a similar role in defining an era.

Intel calls finFETs “tri-gate” transistors, touting them as the first true three-dimensional devices built on planar integrated circuits. A tri-gate transistor folds a conventional planar gate into an inverted U-shaped fin that protrudes above the silicon substrate. By coating all three sides of the fin with metal, Intel builds a 3-D gate structure that has much more volume than a planar gate while still squeezing into the same horizontal space.

Tri-gate transistors can handle greater drive currents, allowing higher clock frequencies. They can switch states at a lower threshold voltage without sacrificing as much switching speed, which reduces dynamic power consumption. In addition, the thicker gate leaks less current, reducing static power. As always, chip designers can trade off these factors in various ways to achieve the best balance of performance and power consumption for the target application.

Intel will use the new transistors for both logic circuits and memory arrays in all its microprocessors built in the next-generation 22nm process, which debuts later this year. The company has demonstrated PC and server processors built with the new technology and is already shipping samples to OEMs for system design. Volume production is scheduled to begin in the fourth quarter and ramp quickly next year. And Intel isn’t hedging its bets: contrary to rumors, the new chips will use tri-gate transistors universally, abandoning planar transistors forever.

FinFETs reinforce Intel’s significant lead in chip fabrication. In addition to using new transistors, Intel is moving to the 22nm mode about two years ahead of the rest of the industry, which is only now beginning the transition to 32/28nm technology. The independent foundries serving virtually all of Intel’s competitors have no plans to use finFETs before the 14nm node—and adoption may be tentative even then. It appears that Intel has gained a head start of at least four years, much as the company achieved in 2007 by introducing high-k metal-gate (HKMG) transistors at the 45nm node. FinFETs could boost Intel’s position in the mobile and consumer markets, where it needs an edge to overcome entrenched competitors. —Tom

Integrated chips fuel smartphone growth [April 19, 2011]

Silicon integration will be the key differentiator in smartphones which could grow to 600 million units in 2014, driven by expansion in low-cost handsets, according to a presentation at the inaugural Linley Tech Mobile Conferencehere.

“The next 300 million smartphones will come from feature phone replacements,” said Linley Gwennap, principal of The Linley Group (Mountain View, Calif.), organizer of the event. “The pressure for smartphone designers will be in reducing systems cost to meet this growing demand for lower cost smartphones and silicon integration is a key,” Gwennap said.

Much of the integration will come from combining application and baseband processors. By 2014 nearly 70 percent of all smartphones will use such integrated chips, up from 40 percent in 2010, Gwennap predicted.

Such chips will be key as designers try to hit prices as low as $100 for smartphones sold in emerging markets. Meanwhile, “the percentage of the market you can address with stand-alone application and baseband processors is slowly diminishing” to about 80 to 100 million units a year, Gwennap said.

Qualcomm and Marvell led the move to integrated application and baseband processors and along with Broadcom and ST Ericsson own the pieces required for next-generation integrated chips, Gwennap said.

Qualcomm is shifting from a four- to a three-chip smartphone set in 2012 with separate devices for digital, RF and analog, he added. However many integrated chips may actually use multiple die in a package.

Quad-core chips too hot

In application processors, dual core is sweeping the market this year. Nvidia led the way with its Tegra 2 processor already shipping in LG smartphones and Motorola tablets. A half a dozen other dual-core mobile processors from all the leading chip makers will ship in systems this year, Gwennap predicted.

In February Nvidia demonstrated its next generation, the quad-core Tegra 3. Freescale and Qualcomm have announced similar products on the horizon.

“Some of the initial quad-core designs will exceed the thermal limits of what you can do in a smartphone, so you will need to throttle them back and then you won’t get the performance you expect,” Gwennap said. “Thus quad-cores will be more successful in tablets initially because of their better heat dissipation” until 28nm versions for smartphones are available, he said.

“Over the next year or two, Nvidia and Qualcomm will duel over the performance lead in apps processors, and TI never quite gets there,” said Gwennap. “Broadcom is aiming for lower performance mainstream tablets and feature phone replacements rather than the high-end luxury market [because] you don’t have to be the performance leader to make it in this market,” he said.

Intel is likely to find a small but significant foothold in smartphones over time, Gwennap said.

“By 2014, we expect Intel to have pretty competitive products on aggressive process technologies that may be enough to get them in a small number of phones but there are big barriers for them in creating a software ecosystem,” he said.

Mobile 3-D graphics are also on a tear moving from dual-core chips this year to quad-core versions soon. However, measuring raw mobile graphics performance remains a challenge, said Gwennap, calling for a mobile graphics benchmark.

The hardware along with new video engines will help process either two 1080-progressive video streams at 24 frames/second for stereo 3-D or 60 frames/s video for picture quality. To handle the load at low power rates will require video engines access system memory directly without going through a host CPU, he said.

Nokia may lag shift to dual-core phones [May 4, 2011]

Nokia may lag the shift to dual-core smartphone processors happening this year for lack of support from Microsoft, its new operating system partner.

Three companies are already shipping dual-core mobile processors and as many as eight will be by the end of the year, according to a talk at the Multicore Expohere. “Just about every high end smartphone” will move to dual-core processors in 2011, said Linley Gwennap, principal of the Linley Group (Mountain View, Calif.).

Microsoft removed multicore support from its Mobile Phone 7 OS, focusing the software only on a single-core Qualcomm chip set in an effort to get it to market quickly, said one source. The company knows it needs to update its mobile software more often than its desktop code, but it’s not clear when it will add multicore support.

Handsets typically have a 12-24 month lifecycle, said Gwennap. The lack of multicore support “could limit Nokia until Microsoft can retrofit the software for dual core,” Gwennap said.

Nokia has long been the leading supplier of cellphones, making its Symbian OS among the most popular mobile software platform. But the handset giant has been slow to respond to the concept of a Web-connected device pioneered by the Apple iPhone.

In the first quarter, Apple lead growth in smartphone unit sales, according to IDC.

Symbian^4 is expected to be released soon supporting multicore processors. However, Nokia recently struck a deal with Accenture to hire its Symbian team as part of a plan to layoff 7,000 people.

The LG Optimus smartphone was the first smartphone to use a multicore chip when it shipped in January, quickly followed by tablets from Motorola and Apple in February and March. Mobile multicore chips coming later this year include (in order of their expected appearance) the Samsung Exynos 4210, Qualcomm MSM8260, ST Ericsson U8500, Marvell Armada 2828 and Broadcom BCM 11311.

“ARM has a dual-core Cortex A9 reference design enabling the chip vendors to ship quickly. Most vendors are using it except Marvell and Qualcomm that designed their own multicore architectures.

The multicore chips will help speed core apps from the OS makers such as browsers, Flash and PDF viewers. They will also be used by third party game developers.

“It will take time for a broad base of multicore mobile software to appear,” said Gwennap.

About 21 percent of mobile devices will use multicore processors in 2011 rising rapidly to 94 percent in 2015, Gwennap estimated. By 2013 more multicore processors will ship in mobile systems than in PCs and servers, he said.

The trend will be accelerated by the arrival in 2012 of dual-core chips based on ARM’s Cortex A5 core replacing single-core Cortex A8 chips in mid-range phones. By 2014, those chips will get packed into low-cost smartphones, said Gwennap.

Serving a purpose: Why the ARM architecture is attracting attention in the server market [Feb 21, 2011] (emphasis in red is mine)

Power consumption in data centres is becoming an increasingly important issue – no surprise when these centres can house tens of thousands of servers. So there is a push towards the development of processors which offer higher performance with lower power consumption.This emerging market is attracting the attention of a number of processor developers, including Marvell. “Marvell is targeting data centres that support cloud computing and which provide web services,” said Linley Gwennap, principal analyst at The Linley Group. “In those cases, there would be some significant interest in what Marvell is doing.”

The latest processor family from Marvell, the Armada XP (Extreme Performance), uses the low power ARM architecture to deliver a 1.6GHz quad core variant that has the processing performance needed for the enterprise market. According to Viren Shah, Marvell’s senior director of marketing for embedded SoCs, the device family is aimed at networking, network attached storage, laser printers and the server market. “The server market is dominated by the x86 [architecture], but ARM is making forays into that segment – and the reason is mainly its low power,” said Shah.

Power is the all important metric. “With the quad core design, our goal is to be sub 10W,” said Shah. This is a noteworthy figure; according to Gwennap, Intel’s Xeon processor consumes around 40W. “Even at that power level, Xeon is not designed as an SoC.” In addition to Xeon, a South Bridge chip and Ethernet controllers would also be needed. Marvell has Sheeva, an ARM based core developed after gaining an architectural license when it acquired Intel’s XScale business in 2006.

Sheeva, which is ARM v6 and v7 instruction set compatible, is a two issue design: either two integer instructions or an integer and floating point are issued each clock cycle. The core also has a limited ability for instruction look ahead, boosting code throughput by reordering the sequence in which instructions are processed.

There are five devices in the Armada XP family: two single core; two dual core; and a quad core, the MV78460 (see fig 1). All are pin compatible, but vary in the on chip peripherals, cache size and the width of the memory interface. Each ARM cpu on the MV78460 has a 32kbyte instruction cache and 32kbyte data cache, while the four cores share a 2Mbyte L2 cache. The other Armada XP SoCs have a 1Mbyte L2 cache. The L2 cache is doubled in size in the MV78460 to maintain processing performance.


Sheeva cores access external memory through a controller, with the processor supporting DDR3 memory clocked at 800MHz. The device has 40bit physical addressing that supports up to 1Tbyte of dram. Three Armada XP SoCs, including the MV78460, support a 32 or 64bit memory data interface, while the rest have a 32bit bus. The MV78460 includes two serial ATA (SATA), four PCI Express and four Gigabit Ethernet (GbE) media access controllers (MACs).

These 10 controllers share 16 6GHz serdes, so the PCI Express controllers could be configured as three x4 ports and one x1 port, while the chip cojuld also support two SATA interfaces and a GbE interface. The Ethernet MAC supports the QSGMII interface such that all four GbE ports can be put onto a single serial link. One design challenge with the MV78460, according to Marvell, was cramming four cores and the I/O peripherals onto an SoC. “We have multiple fast I/O that must coexist in the system,” said Erez Alfiya, an application manager at Marvell. “Contention on one affects the whole system performance.” To this end, an on chip crossbar switch connects the cores and the L2 cache, as well as the peripherals as they access DDR3 memory.

The interface between each core and the L2 cache is 128bit wide and includes a coherency unit, which ensures cache coherency by updating the cache whenever data is written to external memory. The crossbar switch also supports the various on chip blocks. “That is a lot of bandwidth we need to supply to the different I/Os,” said Alfiya.

As an example, he cites the case of a GbE interface being used alongside two PCI Express ports. “You have traffic coming from the Ethernet port and from the two PCI Express ports. You need to balance the traffic and allow DDR access to the three interfaces,” said Alfiya. “We have arbitration between the units because only one unit can access the DDR at any time.” Other on chip peripherals include a security engine and support for VoIP via a time division multiplexing (TDM) interface.

The security engine can encrypt 2Gbit/s data streams using such algorithms as AES and 3DES. With the TDM interface, the SoC supports up to 32 channels of VoIP. Marvell uses several power saving techniques to limit the MV78460’s power consumption to 10W. The device can power down unused cpus and vary the clock frequency dynamically to adapt power consumption to processing load. In sleep mode, the cpus can be turned off while the L2 cache remains powered. In deep sleep mode, the L2 cache is saved in dram before being powered down.

The I/O ports then wake the cpus when data arrives. The GbE MACs are Energy Efficient Ethernet compliant (see NE, 25 January 2011) and support DDR3L. Because DDR3L operates at 1.35V, instead of 1.5V, this can reduce power consumption by up to 20%. The device can run one operating system in symmetric multiprocessing mode or asymmetrically.

The latter is less common for servers, but features more widely in embedded applications, where the cores can run separate operating systems. “By integrating everything onto one chip, Marvell has designed a single chip quad core server,” said Gwennap. This is different to Intel’s approach, where two Xeon multicore chips can be put side by side – a so called two socket server configuration. “You cannot do that with the Marvell chip,” said Gwennap. “Marvell has boiled the whole server down to a chip; if you want to scale it, you have to add a whole new, separate, server.” The Armada XP is currently implemented on TSMC’s 40nm G cmos process, although the roadmap includes an eight core design at the 28nm node. The Sheeva cores will be clocked at 3GHz or more, while the SoC will support 10Gbit Ethernet and the PCI Express 3.0 specification.

But Marvell isn’t the only company looking to bring ARM cores to the server market and ARM is seeding the process with a quad core reference design for the Cortex-A9 architecture, while the basic design for the Cortex-A15 is also quad core (see fig 2). One contender is Calxeda, in which ARM is an investor. It is using a quad core implementation of the Cortex-A9 but, because it is limited to four cores per die, it will probably need to use multiple chips to match the performance of Xeon processors.


But the startup is not providing details on the interconnect or the blocks it plans to integrate. “We are going to see a lot of quad core Cortex-A15 designs coming out in a year or so,” Gwennap concluded.


1 Comment

  1. […] information: TSMC led foundries and their SoC customers against Intel [May 10, 2011] – Qualcomm Snapdragon SoCs with a new way of easy identification [Aug 4, […]

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